Multi-layer silicon photonics apparatus

Patent metadata

Field	Value
Publication number	US-12019270-B2
Application number	US-202017004429-A
Country	US
Kind code	B2
Filing date	Aug 27, 2020
Priority date	Aug 27, 2020
Publication date	Jun 25, 2024
Grant date	Jun 25, 2024

Abstract

Embodiments of the present disclosure are directed to low numerical aperture (NA) optical couplers, or spot size converters, that include a lateral taper section and/or a vertical adiabatic taper section. In embodiments, the optical couplers may be positioned on a silicon substrate proximate to V-grooves within the substrate to contain optical fibers to self-align and to couple with the optical couplers. Other embodiments may be described and/or claimed.

First claim

We claim:

1. A silicon photonics integrated apparatus, comprising:
a first layer with a first side (S 11 ) and a second side (S 12 ) opposite the first side (S 11 ) that are substantially parallel, the first side (S 11 ) including an embedded optical interface extending partially down a length a of a center plane of the first layer from a front side of the first layer that is substantially perpendicular to the first side (S 11 ) and the second side (S 12 );
a second layer having a first side (S 21 ) and a second side (S 22 ) opposite the first side (S 21 ) that are substantially parallel, the first side (S 21 ) being coupled with the second side (S 22 ), the first layer overlapping the second layer, and the second layer being symmetrical along the center plane; and
a third layer having a first side (S 31 ) and a second side (S 32 ) opposite the first side (S 31 ), the first side (S 31 ) being coupled with the second side (S 32 );
wherein the second layer forms a rectangular cross section perpendicular to the center plane at width iv/at the front side of the first layer, and extending down a length b of the center plane where b is greater than a;
wherein the second layer further forms a lateral taper away from the center plane from length b to length c, with a rectangular cross section perpendicular to the center plane at length c having a width w 2 , where w 2 is greater than w 1 ;
the third layer does not overlap a portion of the second layer, and the third layer is symmetrical along the center plane; and
wherein the third layer further forms a lateral taper away from the center plane from length c to length d, with a rectangular cross-section perpendicular to the center plane at length c having a width w 3 , where w 3 is less than or equal to w 2 , and a width of the rectangular cross-section perpendicular to the center plane at length d is w 4 , where w 4 is greater than w 3 .

2. The apparatus of claim 1 , further comprising wherein the first side (S 31 ) and the second side (S 32 ) are substantially parallel.

3. The apparatus of claim 1 , wherein the third layer further forms a vertical taper away from the first side (S 31 ).

4. The apparatus of claim 1 , wherein the first, second and third layers are waveguide layers.

5. The apparatus of claim 1 , wherein the first, second and third layers are silicon nitride (SiN) layers or silicon oxy nitride layers.

6. The apparatus of claim 1 , wherein w 3 =w 2 .

7. A method for manufacturing a silicon photonics integrated apparatus, the method comprising:
applying a first layer having a first side (S 11 ) and a second side (S 12 ) opposite the first side (S 11 ) that are substantially parallel, the first side (S 11 ) including an embedded optical interface extending partially down a length a of a center plane of the first layer from a front side of the first layer that is substantially perpendicular to the first side (S 11 ) and the second side (S 12 );
applying a second layer to the first layer, the second layer having a first side (S 21 ) and a second side (S 22 ) opposite the first side (S 21 ) that are substantially parallel, the first side (S 21 ) being coupled with the second side (S 22 ), the first layer overlapping the second layer, and the second layer being symmetrical along the center plane;
applying a third layer to the second layer, the third layer having a first side (S 31 ) and a second side (S 32 ) opposite the first side (S 31 ), the first side (S 31 ) being coupled with the second side (S 32 );
wherein the second layer forms a rectangular cross section perpendicular to the center plane at width w 1 at the front side of the first layer, and extending down a length b of the center plane where b is greater than a,
wherein the second layer further forms a lateral taper away from the center plane from length b to length c, with a rectangular cross section perpendicular to the center plane at length c having a width w 2 , where w 2 is greater than w 1 ;
wherein the third layer does not overlap a portion of the second layer, and the third layer is symmetrical along the center plane; and
wherein the third layer further forms a lateral taper away from the center plane from length c to length d, with a rectangular cross-section perpendicular to the center plane at length c having a width w 3 , where w 3 is less than or equal to w 2 , and a width of the rectangular cross-section perpendicular to the center plane at length d is w 4 , where w 4 is greater than w 3 .

8. The method of claim 7 , further comprising, prior to applying the first layer, applying a buried oxide layer; and wherein the first layer is applied to the buried oxide layer.

9. The method of claim 8 , wherein the buried oxide layer is coupled with a substrate.

10. The method of claim 7 , further comprising wherein the first side (S 31 ) and the second side (S 32 ) are substantially parallel.

11. The method of claim 7 , wherein the third layer further forms a vertical taper away from the first side (S 31 ).

12. The method of claim 7 , wherein the first, second, and third layers are silicon nitride (SiN) layers or silicon oxy nitride layers.

13. The method of claim 7 , wherein w 3 =w 2 .

Assignees

• Intel Corp

Inventors

• Mahalingam Hari
• Frish Harel
• Mccargar Sean
• Keener Joshua
• Yerkes Shane
• Heck John
• Liao Ling

Classifications

• G02B6/305 Primary

  and having an integrated mode-size expanding section, e.g. tapered waveguide · CPC title

• G02B6/26

  Optical coupling means (G02B6/36, G02B6/42 take precedence) · CPC title

• G02B6/13

  Integrated optical circuits characterised by the manufacturing method · CPC title

• G02B6/1228 Primary

  Tapered waveguides, e.g. integrated spot-size transformers (for coupling with fibres G02B6/305) · CPC title

• G02B6/136

  by etching · CPC title