Method for fabricating a semiconductor device using wet etching and dry etching and semiconductor device

Patent metadata

Field	Value
Publication number	US-12018387-B2
Application number	US-202217582656-A
Country	US
Kind code	B2
Filing date	Jan 24, 2022
Priority date	Jan 25, 2021
Publication date	Jun 25, 2024
Grant date	Jun 25, 2024

Abstract

A method for fabricating a semiconductor device comprises depositing a TiW layer on a semiconductor substrate, depositing a Ti layer on the TiW layer, depositing a Ni alloy layer on the Ti layer, depositing an Ag layer on the Ni alloy layer, at least partially covering the Ag layer with photoresist, wet etching the Ag layer and the Ni alloy layer, and dry etching the Ti layer and the TiW layer.

First claim

The invention claimed is:

1. A method for fabricating a semiconductor device, the method comprising:
depositing a TiW layer on a semiconductor substrate,
depositing a Ti layer on the TiW layer,
depositing a Ni alloy layer on the Ti layer,
depositing an Ag layer on the Ni alloy layer,
at least partially covering the Ag layer with photoresist,
wet etching the Ag layer and the Ni alloy layer, and
dry etching the Ti layer and the TiW layer,
wherein the Ag layer, the Ni alloy layer, the Ti layer and the TiW layer form a layer stack, and
wherein as viewed from above the Ag layer, after the dry etching, the Ti layer and the TiW layer of the layer stack have a greater lateral extension than the Ag layer and the Ni alloy layer of the layer stack, such that the layer stack is free of any undercuts between different layers of the layer stack.

2. The method of claim 1 , wherein the wet etching is done using a solution comprising phosphoric acid, acetic acid and nitric acid.

3. The method of claim 1 , wherein the dry etching is done using a gas comprising chlorine and fluorine.

4. The method of claim 1 , further comprising:
during the dry etching, spectroscopically analyzing an exhaust gas for residues removed by the dry etching, and
stopping the dry etching once residues of the semiconductor substrate or of a further layer arranged between the semiconductor substrate and the TiW layer are detected in the exhaust gas.

5. The method of claim 1 , wherein the dry etching is performed within no more than 12 hours of the wet etching.

6. The method of claim 1 , wherein the photoresist is applied only once and is used for both the wet etching and the dry etching.

7. The method of claim 1 , wherein between the wet etching and the dry etching, the photoresist is removed and then re-applied.

8. The method of claim 1 , further comprising:
arranging an imide layer between the semiconductor substrate and the TiW layer.

9. The method of claim 1 , wherein the Ni alloy is selected from the group comprising NiV, NiSi and NiN.

10. The method of claim 1 , wherein at least one of the TiW layer, the Ti layer, the Ni alloy layer, and the Ag layer comprise respective side faces arranged at an angle with respect to a first main side of the semiconductor substrate.

11. The method of claim 10 , wherein the angle of the respective side faces of the Ni alloy layer is a first angle, the angle of the respective side faces of the Ag layer is a second angle, the angle of the respective side faces of the Ti layer is a third angle, and the angle of the respective side faces of the TiW layer is a fourth angle.

Assignees

• Infineon Technologies Austria Ag

Inventors

• Roy Saurabh
• Dainese Matteo
• Ehmann Michael
• Narahashi Hiroshi
• Schlaminger Johanna
• Teichmann Katharina
• Wabnig Sigrid

Classifications

• H10P50/667 Primary

  by liquid etching only · CPC title

• H10W72/073

  of die-attach connectors · CPC title

• H10W72/59

  Bond pads specially adapted therefor · CPC title

• H10W72/90

  Bond pads, in general · CPC title

• H10W72/30

  Die-attach connectors · CPC title