Method of manufacturing printed circuit board

Patent metadata

Field	Value
Publication number	US-12016130-B2
Application number	US-202217683604-A
Country	US
Kind code	B2
Filing date	Mar 1, 2022
Priority date	May 26, 2021
Publication date	Jun 18, 2024
Grant date	Jun 18, 2024

Abstract

A method of manufacturing a printed circuit board includes: forming a resist layer; exposing first areas of the resist layer spaced apart from each other; after exposing the first areas, exposing second areas of the resist layer, the second areas being spaces between the first areas; forming first and second openings spaced apart from each other in the first and second areas by developing the resist layer; and forming a plurality of conductor patterns by filling the first and second openings with conductors.

First claim

What is claimed is:

1. A method of manufacturing a printed circuit board, the method comprising:
forming a resist layer;
exposing first areas of the resist layer spaced apart from each other;
after exposing the first areas, exposing second areas of the resist layer, the second areas being spaces between the first areas;
forming first and second openings spaced apart from each other in the first and second areas by developing the resist layer; and
forming a plurality of conductor patterns by filling the first and second openings with conductors,
wherein the first openings include a 1-1st opening and a 1-2nd opening spaced apart from each other,
the second openings include a 2-1st opening and a 2-2nd opening spaced apart from each other,
the plurality of conductor patterns include a 1-1st conductor pattern formed in the 1-1st opening, a 1-2nd conductor pattern formed in the 1-2nd opening, a 2-1st conductor pattern formed in the 2-1st opening, and a 2-2nd conductor pattern formed in the 2-2nd opening,
when the plurality of conductor patterns are taken in cross sections thereof in a thickness direction, each of W P1-1 , W P1-2 , W P2-1 , and W P2-2 is 0.5 μm or more and 5 μm less, where W P1-1 is an average line width of the 1-1st conductor pattern, W P2-1 is an average line width of the 2-1st conductor pattern, W P1-2 is an average line width of the 1-2nd conductor pattern, and W P2-2 is an average line width of the 2-2nd conductor pattern, and
a ratio of a width of each of spaces between the 1-1st, 2-1st, 1-2nd, and 2-2nd conductor patterns with respect to an average height of the 1-1st, 2-1st, 1-2nd, and 2-2nd conductor patterns is more than ¼ and less than ⅗.

2. The method of claim 1 , wherein in the exposing of the second areas of the resist layer, the second areas are exposed so that the first areas are included in non-exposed areas between the second areas spaced apart from each other.

3. The method of claim 2 , further comprising forming a seed layer before the forming of the resist layer,
wherein the forming of the plurality of conductor patterns includes:
forming a plating layer on the seed layer exposed through the first and second openings by electroplating;
removing the resist layer; and
removing the seed layer.

4. The method of claim 3 , wherein the forming of the plating layer on the seed layer exposed through the first and second openings by electroplating includes:
performing over-plating so that the plating layer exceeds a thickness of the resist layer; and
polishing an over-plated area of the plating layer exceeding the thickness of the resist layer.

5. The method of claim 3 , wherein the seed layer is a metal layer attached onto one surface of an insulating material,
the resist layer is formed on the metal layer,
the forming of the plurality of conductor patterns further includes forming an insulating layer on the metal layer to cover the plating layer between the removing of the resist layer and the removing of the seed layer, and
the removing of the seed layer includes:
removing the insulating material from the metal layer; and
removing the metal layer attached onto the insulating layer.

6. The method of claim 1 , wherein the second areas and the first areas are alternately disposed.

7. The method of claim 1 , wherein when the plurality of conductor patterns are taken in the cross sections thereof in the thickness direction, each of S 1 to S 3 is 0.5 μm or more and 5 μm or less,
where S 1 is an average space between the 1-1st conductor pattern and the 2-1st conductor pattern, S 2 is an average space between the 2-1st conductor pattern and the 1-2nd conductor pattern, and S 3 is an average space between the 1-2nd conductor pattern and the 2-2nd conductor pattern.

8. The method of claim 7 , wherein S 1 and S 3 satisfy 0.9<S 1 /S 3 <1.1.

9. The method of claim 8 , wherein a value obtained by dividing an absolute value of a difference between S 1 and S 2 by S 1 is more than 0.1.

10. The method of claim 1 , wherein W P1-1 and W P1-2 satisfy 0.9<W P1-1 /W P1-2 <1.1.

11. The method of claim 10 , wherein a value obtained by dividing an absolute value of a difference between W P1-1 and W P2-1 by W P1-1 is more than 0.1.

12. The method of claim 1 , wherein when the plurality of conductor patterns are taken in the cross sections thereof in the thickness direction, H P1-1 and H P1-2 satisfy 0.9<H P1-1 /H P1-2 <1.1,
where H P1-1 is an average height of the 1-1st conductor pattern, H P2-1 is an average height of the 2-1st conductor pattern, and H P1-2 is an average height of the 1-2nd conductor pattern.

13. The method of claim 12 , wherein a value obtained by dividing an absolute value of a difference between H P1-1 and H P2-1 by H P1-1 is more than 0.1.

Assignees

• Samsung Electro Mech

Inventors

• Park Chan Jin
• Park Jong Eun
• Yang Hyun Seok
• Cho Sangik
• Okada Hiroki
• Cho Young Ook
• Jeon Mi Jeong
• Chung In Jae

Classifications

• C25D5/022

  using masking means · CPC title

• G03F7/20

  Exposure; Apparatus therefor (photographic printing apparatus for making copies G03B27/00) · CPC title

• H05K2203/025

  Abrading, e.g. grinding or sand blasting · CPC title

• C25D7/00

  Electroplating characterised by the article coated · CPC title

• H05K2203/1476

  Same or similar kind of process performed in phases, e.g. coarse patterning followed by fine patterning · CPC title