Apparatus for compensating parasitic impedance for integrated circuits

Patent metadata

Field	Value
Publication number	US-12015243-B2
Application number	US-202217720139-A
Country	US
Kind code	B2
Filing date	Apr 13, 2022
Priority date	Jan 16, 2019
Publication date	Jun 18, 2024
Grant date	Jun 18, 2024

Abstract

A laser diode driver circuit includes a first pair of contacts and connectors coupled to an anode of the laser diode. An inductance of each of the first pair of contacts and connectors is the same. A second pair of contacts and connectors are coupled to a cathode of the laser diode. An inductance of each of the second pair of contacts and connectors is the same. The laser diode driver circuit also includes current driving circuitry.

First claim

The invention claimed is:

1. A laser diode driver circuit comprising:
a plurality of connection paths including:
a first pair of connection paths each coupled to an anode of a laser diode, the first pair of connection paths including a first connection path and a second connection path, a first inductance of the first connection path being substantially equal to a second inductance of the second connection path; and
a second pair of connection paths each coupled to a cathode of the laser diode, the second pair of connection paths including a third connection path and a fourth connection path, a third inductance of the third connection path being substantially equal to a fourth inductance of the fourth connection path; and

current driving circuitry, configured to drive one or more current passing through one or more connection paths of the plurality of connection paths, the current driving circuitry including:
a first switch configured to selectively couple the first connection path to a high potential supply node;
a first diode having a cathode coupled to the high potential supply node and an anode:
a first current source configured to provide a first current and
a second switch configured to selectively couple the second connection path to the anode of the first diode or to a low potential supply node via the first current source.

2. The laser diode driver circuit according to claim 1 , wherein the first switch includes a pMOS transistor coupled to be controlled by a safety control signal.

3. The laser diode driver circuit according to claim 1 , wherein the second switch includes an nMOS transistor coupled to be controlled by an anode control signal.

4. The laser diode driver circuit according to claim 1 , wherein the current driving circuitry further includes:
a second diode having an anode coupled to the low potential supply node and a cathode;
a third switch configured to selectively couple the third connection path to the cathode of the second diode or to the high potential supply node.

5. The laser diode driver circuit according to claim 4 , wherein the third switch includes a nMOS transistor coupled to be controlled by a cathode control signal.

6. The laser diode driver circuit according to claim 4 , wherein the current driving circuitry further includes:
a second current source configured to provide a second current; and
a fourth switch configured to selectively couple the fourth connection path to the second current source or to the high potential supply node.

7. The laser diode driver circuit according to claim 6 , wherein the third switch includes a pMOS transistor coupled to be controlled by a second cathode control signal.

8. The laser diode driver circuit according to claim 1 , further comprising:
timing generating circuitry configured to generate four phase-shifted clock signals;
a combinational logic configured to receive the four phase-shifted clock signals and to generate phase-defining signals for defining a start of a first phase, a start of a second phase and a start of a third phase, respectively, wherein the phase-defining signals are generated based on one of rising edges of the four phase-shifted clock signals and falling edges of the four phase-shifted clock signals; and
a level shifter for receiving the phase-defining signals and for outputting signals for controlling the current driving circuitry to operate in the first phase, the second phase and the third phase.

9. The laser diode driver circuit according to claim 8 , wherein the timing generating circuitry is configured to generate:
a first clock signal;
a second clock signal, which is a first phase-shifted version of the first clock signal;
a third clock signal, which is a second phase-shifted version of the first clock signal; and
a fourth clock signal, which is a third phase-shifted version of the first clock signal.

10. The laser diode driver circuit according to claim 1 , wherein each connection path of the plurality of connection paths includes a connection wiring and a connection pad.

11. A method, comprising:
operating a laser diode driver circuit in a first phase of driving a laser diode, wherein:
a first current passes through a first pair of connection paths of the laser diode driver circuit, the first pair of connection paths coupled to an anode of the laser diode and including a first connection path and a second connection path, and
a second current passes through a second pair of connection paths of the laser diode driver circuit, the second pair of connection paths coupled to a cathode of the laser diode and including a third connection path and a fourth connection path, and
a potential difference between the cathode and the anode is below a diode activation value;

operating the laser diode driver circuit in a second phase of driving the laser diode subsequent to the first phase, wherein:
the second current passes through the first connection path of the first pair of connection paths, the laser diode and the third connection path of the second pair of connection paths, and
the potential difference between the cathode and the anode is above the diode activation value; and

operating the laser diode driver circuit in a third phase of driving the laser diode subsequent to the second phase, wherein:
a third current passes through the first connection path of the first pair of connection paths, the laser diode and the third connection path of the second pair of connection paths, and
the potential difference between the cathode and the anode is below the diode activation value.

12. The method according to claim 11 , further comprising:
generating four phase shifted clock signals;
generating phase defining signals for defining a start of the first phase, a start of the second phase and a start of the third phase, the phase defining signals being generated based on one of rising edges of the four phase shifted clock signals and falling edges of the four phase shifted clock signals; and
generating output signals based on the phase defining signals for controlling current driving circuitry to operate in the first phase, the second phase and the third phase.

13. The method according to claim 12 , further comprising generating:
a first clock signal;
a second clock signal, which is a first phase-shifted version of the first clock signal;
a third clock signal, which is a second phase-shifted version of the first clock signal, sequential falling or rising edges of the first clock signal and the third clock signal defining the passing of the first current through the first pair of connection paths, and sequential falling or rising edges of the second clock signal and the third clock signal defining the passing of the second current through the second pair of connection path; and
a fourth clock signal, which is a third phase-shifted version of the first clock signal, a falling or rising edge of the third clock signal and a rising or falling edge of the fourth clock signal defining the passing of the second current through the first connection path of the first pair of connection paths, the laser diode and the third connection path of the second pair of connection path.

14. A driver circuit, comprising:
a first pair of connection paths configured to be coupled to a first terminal of a device, the first pair of connection paths including a first connection path having a first inductance and a second connection path having a second inductance;
a second pair of connection paths configured to be coupled to a second terminal of the device, the second pair of connection paths including a third connection path

Assignees

• St Microelectronics Res & Dev Ltd
• St Microelectronics Grenoble 2

Inventors

• Lee Denise Tingxi
• Dutton Neale
• Moeneclaey Nicolas
• Andriot-Ballet Jerome

Classifications

• H01S5/183

  having only vertical cavities, e.g. vertical cavity surface-emitting lasers [VCSEL] · CPC title

• H01S5/042

  Electrical excitation {; Circuits therefor (monolithically integrated laser drive components H01S5/0261)} · CPC title

• H01S5/06226

  Modulation at ultra-high frequencies · CPC title

• H01S5/0261 Primary

  Non-optical elements, e.g. laser driver components, heaters (H01S5/0265 takes precedence) · CPC title

• H01S5/0428 Primary

  for applying pulses to the laser · CPC title