Display substrate, display panel and display device, of each of which a pixel electrode having a hollowed-out structure with a preset size

Patent metadata

Field	Value
Publication number	US-12014696-B2
Application number	US-202117773531-A
Country	US
Kind code	B2
Filing date	May 20, 2021
Priority date	Jun 30, 2020
Publication date	Jun 18, 2024
Grant date	Jun 18, 2024

Abstract

A display substrate includes: a first base substrate ( 20 ), and gate lines ( 4 ) and data lines ( 5 ) on the first base substrate ( 20 ). The gate lines ( 4 ) extend in a first direction (X), and the data lines ( 5 ) extend in a second direction (Y). The gate lines ( 4 ) and the data lines ( 5 ) define pixel units, each of which includes a thin film transistor ( 7 ), a pixel electrode ( 8 ) and a common electrode ( 9 ). At least some of the pixel units are respectively configured with conductive bridge lines ( 10 ) provided in the same layer as the pixel electrode ( 8 ). In a pixel unit configured with the conductive bridge line ( 10 ), a first hollowed-out structure ( 13 ) and a second hollowed-out structure ( 14 ) are provided on opposite sides of the pixel electrode ( 8 ) in the first direction, to weaken or even eliminate mura (e.g., nonuniformity in brightness or color).

First claim

What is claimed is:

1. A display panel, comprising: a display substrate and an opposite substrate arranged oppositely, and a liquid crystal layer being filled between the display substrate and the opposite substrate, wherein the display substrate comprises: a first base substrate, and a plurality of gate lines and a plurality of data lines, which are on the first base substrate, wherein the gate lines extend in a first direction, the data lines extend in a second direction, the first direction and the second direction intersect each other and are both parallel to a plane where the first base substrate is located;
the plurality of gate lines and the plurality of data lines define a plurality of pixel units, each of the pixel units comprises a thin film transistor, a pixel electrode and a common electrode, the pixel electrode is on a side of the common electrode distal to the first substrate; in a same pixel unit, a region where the pixel electrode is located and a region where the thin film transistor is located are arranged in the second direction, an end of the pixel electrode proximal to the thin film transistor is a first end, an end of the pixel electrode distal to the thin film transistor is a second end; at least some of the pixel units are configured with conductive bridge lines, respectively, the conductive bridge lines are provided in the same layer as the pixel electrode;
in the pixel unit which is configured with the conductive bridge line, a first hollowed-out structure is provided on a first side of the first end or the second end of the pixel electrode, an end of the conductive bridge line is located in the first hollowed-out structure and is connected to the common electrode through a via, and a second hollowed-out structure is provided on a second side of the second end of the pixel electrode, so that an absolute value of a difference between parasitic capacitances formed respectively by the pixel electrode and nearest data lines located on both sides of the pixel electrode is less than or equal to a preset capacitance difference;
the first side and the second side are opposite sides of the pixel electrode in the first direction;
wherein, for any one of the pixel units, a polarity of a data voltage applied to a nearest data line on a side of the pixel electrode is inverted, and an amount of change in a voltage applied to the pixel electrode in the pixel unit due to the polarity inversion is ΔVp:
Δ Vp=Cpd 1*Δ Vd /( Cpd 1+ Cpd 2+ Cst+Clc+Cgp )

where Cpd1 represents a parasitic capacitance formed between the pixel electrode in the pixel unit and the data line where the polarity inversion occurs, ΔVd represents a difference between the data voltage applied after the polarity inversion and the data voltage applied before the polarity inversion on the data line where the polarity inversion occurs, Cpd1+Cpd2 represents a sum of parasitic capacitances formed respectively between the pixel electrode in the pixel unit and nearest data lines located on both sides of the pixel electrode, Cst represents a storage capacitance between the pixel electrode in the pixel unit and the common electrode, Clc represents a liquid crystal capacitance at the pixel unit, and Cgp represents a parasitic capacitance between the pixel electrode in the pixel unit and the gate line;
wherein the opposite substrate is a color filter substrate which comprises: a second base substrate, and color filter patterns and a black matrix which are located on the second base substrate;
the black matrix defines multiple pixel light outgoing openings being in one-to-one correspondence with the pixel units, and the color filter patterns are located in the pixel light outgoing openings, respectively; and
an orthogonal projection of the black matrix on the first base substrate completely covers orthogonal projections of the gate lines, the data lines, the thin film transistor, the first hollowed-out structure and the second hollowed-out structure on the first base substrate.

2. The display panel of claim 1 , wherein the thin film transistor in each pixel unit is electrically connected to the data line located on the second side of the pixel unit;
the pixel unit comprises: a red pixel unit, a green pixel unit and a blue pixel unit;
a shape of a pixel opening corresponding to the red pixel unit comprises: a first rectangular portion, and a first protrusion and a second protrusion formed by extending two corner regions of the first rectangular portion located on the second side outward along the second direction;
a shape of a pixel opening corresponding to the green pixel unit comprises: a second rectangular portion, and a third protrusion and a fourth protrusion formed by extending two corner regions of the second rectangular portion located on the first side outward along the second direction; and
a shape of a pixel opening corresponding to the blue pixel unit comprises: a third rectangular portion; or
a shape of the pixel opening corresponding to the blue pixel unit comprises: a third rectangular portion, a fifth protrusion formed by extending a corner region of the third rectangular portion on the first side and also located on a third side outward along the second direction, and a sixth protrusion formed by extending a corner region of the third rectangular portion on the second side and also located on a fourth side outward along the second direction, wherein the third side and the fourth side are two opposite sides of the third rectangular portion in the second direction.

3. The display panel of claim 1 , wherein in the display substrate, each of some of the pixel units is provided with a first limit block and a second limit block, each of the some of the pixel units has a preset light outgoing region, and the first limit block and the second limit block are located at two opposite sides of the preset light outgoing region in the second direction, respectively;
each of the first limit block and the second limit block comprises a first limiting pattern and a second limiting pattern that are stacked together, the first limiting pattern is arranged in the same layer as the gate lines, and the second limiting pattern is arranged in the same layer as the data lines;
all the pixel units in the display substrate comprise: a red pixel unit, a green pixel unit and a blue pixel unit; and
the red pixel unit is provided with the first limit block and the second limit block; and
the color filter substrate further comprises a spacer, the spacer is located on a side of the black matrix distal to the second base substrate, a projection of the spacer on the display substrate is located between a first limit block and a second limit block adjacent to each other in the second direction, and the first and second limit blocks adjacent to each other are located in two pixel units adjacent to each other in the second direction, respectively.

4. A display device, comprising the display panel of claim 1 .

5. The display panel of claim 1 , wherein a length of the second hollowed-out structure in the second direction is equal to that of the first hollowed-out structure in the second direction.

6. The display panel of claim 1 , wherein a length of the second hollowed-out structure in the first direction is less than or equal to that of the first hollowed-out structure in the first direction.

7. The display panel of claim 1 , wherein the parasitic capacitances formed respectively by the pixel electrode and the nearest data lines located on both sides of the pixel electrode are equal to each other.

8. The display panel of claim 1 , wherein multiple pixel units arranged in the first direction correspond to a same strip-shaped common electrode, and the strip-shaped common electrode extends in the first directi

Assignees

• Beijing Boe Display Tech Co
• Boe Technology Group Co Ltd

Inventors

• Su Qiujie

Classifications

• H10D86/441

  Interconnections, e.g. scanning lines · CPC title

• H10D86/60

  wherein the TFTs are in active matrices · CPC title

• G09G2320/0233

  Improving the luminance or brightness uniformity across the screen · CPC title

• G09G2300/0842

  forming a memory circuit, e.g. a dynamic memory with one capacitor · CPC title

• G09G2300/0452

  Details of colour pixel setup, e.g. pixel composed of a red, a blue and two green components · CPC title