Vector computation unit in a neural network processor

US12014272B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-12014272-B2
Application numberUS-202318176640-A
CountryUS
Kind codeB2
Filing dateMar 1, 2023
Priority dateMay 21, 2015
Publication dateJun 18, 2024
Grant dateJun 18, 2024

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  1. Title

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  2. Abstract

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  5. First independent claim

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Abstract

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A circuit for performing neural network computations for a neural network comprising a plurality of layers, the circuit comprising: activation circuitry configured to receive a vector of accumulated values and configured to apply a function to each accumulated value to generate a vector of activation values; and normalization circuitry coupled to the activation circuitry and configured to generate a respective normalized value from each activation value.

First claim

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The invention claimed is: 1. A vector computation unit for performing neural network computations comprising: activation circuitry configured to: receive a vector of accumulated values; receive one or more control signals specifying an activation function; and apply the activation function to the accumulated values to generate a vector of activation values; and pooling circuitry configured to: receive the activation values; receive the one or more control signals specifying a pooling function; and apply the pooling function to the activation values to generate a pooled value. 2. The vector computation unit of claim 1 , wherein the one or more control signals are provided by a sequencer. 3. The vector computation unit of claim 1 , wherein the accumulated values correspond to products of a matrix multiplication between a layer of the neural network and a parameter matrix for the layer. 4. The vector computation unit of claim 1 , further comprising normalization circuitry configured to: receive the activation values; receive the one or more control signals specifying a normalization function; and apply the normalization function to the activation values to generate respective normalized values for each activation value. 5. The vector computation unit of claim 4 , wherein the pooling circuitry is further configured to: receive the normalized values; and apply the pooling function to the normalized values to generate the pooled value. 6. The vector computation unit of claim 1 , wherein the pooled value comprises at least one of a maximum, a minimum, or an average of the activation values, or a maximum, a minimum, or an average of a subset of the activate values. 7. The vector computation unit of claim 1 , wherein the pooling circuitry comprises multiple parallel pooling circuitries, each pool circuitry configured to receive a subset of the activation values to generate a respective pooled value. 8. The vector computation unit of claim 1 , further comprising a plurality of registers and a plurality of memory units configured to store the activation values. 9. A method for performing neural network computations comprising: receiving, by activation circuitry, a vector of accumulated values and one or more control signals specifying an activation function; applying, by the activation circuitry, the activation function to the accumulated values to generate a vector of activation values; receiving, by pooling circuitry, the activation values and the one or more control signals specifying a pooling function; and applying, by the pooling circuitry, the pooling function to the activation values to generate a pooled value. 10. The method of claim 9 , wherein the one or more control signals are provided by a sequencer. 11. The method of claim 9 , wherein the accumulated values correspond to products of a matrix multiplication between a layer of the neural network and a parameter matrix for the layer. 12. The method of claim 9 , further comprising: receiving, by normalization circuitry, the activation values and the one or more control signals specifying a normalization function; and applying, by the normalization circuitry, the normalization function to the activation values to generate respective normalized values for each activation value. 13. The method of claim 12 , further comprising: receiving, by the pooling circuitry, the normalized values; and applying, by the pooling circuitry, the pooling function to the normalized values to generate the pooled value. 14. The method of claim 9 , wherein the pooled value comprises at least one of a maximum, a minimum, or an average of the activation values, or a maximum, a minimum, or an average of a subset of the activate values. 15. The method of claim 9 , wherein the pooling circuitry comprises multiple parallel pooling circuitries, each pool circuitry configured to receive a subset of the activation values to generate a respective pooled value. 16. The method of claim 9 , further comprising storing the activation values in a plurality of registers and a plurality of memory units. 17. A non-transitory computer readable medium for storing instructions executable by a processor to perform neural network computations, the instructions comprising: receiving, by activation circuitry, a vector of accumulated values and one or more control signals specifying an activation function; applying, by the activation circuitry, the activation function to the accumulated values to generate a vector of activation values; receiving, by pooling circuitry, the activation values and the one or more control signals specifying a pooling function; and applying, by the pooling circuitry, the pooling function to the activation values to generate a pooled value. 18. The non-transitory computer readable medium of claim 17 , wherein the instructions further comprise: receiving, by normalization circuitry, the activation values and the one or more control signals specifying a normalization function; and applying, by the normalization circuitry, the normalization function to the activation values to generate respective normalized values for each activation value. 19. The non-transitory computer readable medium of claim 18 , wherein the instructions further comprise: receiving, by the pooling circuitry, the normalized values; and applying, by the pooling circuitry, the pooling function to the normalized values to generate the pooled value. 20. The non-transitory computer readable medium of claim 17 , wherein the instructions further comprise storing the activation values in a plurality of registers and a plurality of memory units.

Assignees

Inventors

Classifications

  • G06N3/08Primary

    Learning methods · CPC title

  • Feedforward networks · CPC title

  • Convolutional networks [CNN, ConvNet] · CPC title

  • Inference or reasoning models · CPC title

  • for evaluating functions by calculation {(G06F7/4824 takes precedence)} · CPC title

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What does patent US12014272B2 cover?
A circuit for performing neural network computations for a neural network comprising a plurality of layers, the circuit comprising: activation circuitry configured to receive a vector of accumulated values and configured to apply a function to each accumulated value to generate a vector of activation values; and normalization circuitry coupled to the activation circuitry and configured to gener…
Who is the assignee on this patent?
Google Llc
What technology area does this patent fall under?
Primary CPC classification G06N3/08. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Jun 18 2024 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 6 related publications on this page (citations in our corpus or others sharing the same primary CPC).