Two-stage vector reduction using two-dimensional and one-dimensional systolic arrays

Patent metadata

Field	Value
Publication number	US-2016267111-A1
Application number	US-201514715557-A
Country	US
Kind code	A1
Filing date	May 18, 2015
Priority date	Mar 11, 2015
Publication date	Sep 15, 2016
Grant date	—

Abstract

Examples of the disclosure efficiently processing data sets. In some examples, a plurality of first processor elements process a first data set (e.g., an image) and a second data set (e.g., a kernel) using a first function to generate a third data set. The third data set is processed using a second function to generate an output element. The first processor elements are arranged in a two-dimensional systolic array such that one or more first processor elements receive input from a first adjacent first processor element and transmit output to a second adjacent first processor element. A plurality of second processor elements aggregate the output element to at least partially generate a fourth data set. The plurality of second processor elements arranged in a one-dimensional array. Aspects of the disclosure facilitate increasing speed, conserving memory, reducing processor load or an amount of energy consumed, and/or reducing network bandwidth usage.

First claim

What is claimed is:

1 . A system comprising:
a plurality of first processor elements configured to process a first data set and a second data set using a first function to generate a third data set, and process the third data set using a second function to generate an output element, the plurality of first processor elements arranged in a two-dimensional systolic array such that one or more first processor elements of the plurality of first processor elements are configured to receive input from one or more first adjacent first processor elements and transmit output to one or more second adjacent first processor elements; and a plurality of second processor elements configured to aggregate the output element to at least partially generate a fourth data set, the plurality of second processor elements arranged in a one-dimensional array.

2 . The system of claim 1 , further comprising a sensor module configured to capture data corresponding to one or more images, and transmit the one or more images towards the plurality of first processor elements, the first data set associated with the one or more images.

3 . The system of claim 1 , wherein the second data set is associated with a filter.

4 . The system of claim 1 , wherein the plurality of first processor elements are configured to retrieve the first data set from a memory area, the first data set and the third data set processed locally at the system without transmitting data to or retrieving additional data from the memory area.

5 . The system of claim 1 , wherein the plurality of first processor elements are arranged in a plurality of rows, a first row of the plurality of rows associated with a first element of the first data set.

6 . The system of claim 1 , wherein the plurality of first processor elements are arranged in a plurality of columns, a first column of the plurality of columns associated with a first element of the second data set.

7 . The system of claim 1 , wherein one or more first processor elements of the plurality of first processor elements are configured to sequentially process a plurality of elements included in the first data set.

8 . The system of claim 1 , wherein one or more first processor elements of the plurality of first processor elements are configured to process a first element included in the first data set sequentially using a plurality of second elements included in the second data set.

9 . The system of claim 1 , wherein one or more of the plurality of first processor elements and the plurality of second processor elements are modifiable to modify a rate at which one or more of the output element and the fourth data set are generated.

10 . A method of processing a data set using a processor module including a two-dimensional array and a one-dimensional array, the two-dimensional array including a plurality of first processor elements, the one-dimensional array including a plurality of second processor elements, the method comprising:
processing, at the two-dimensional array, a first data set and a second data set using a first function to generate a third data set, one or more processor elements of the two-dimensional array receiving input from one or more first adjacent processor elements of the two-dimensional array and transmitting output to one or more second adjacent processor elements of the two-dimensional array; processing, at the two-dimensional array, the third data set using a second function to generate an output element; and aggregating, at the one-dimensional array, the output element to at least partially generate a fourth data set.

11 . The method of claim 10 , further comprising generating, at a sensor module, one or more images associated with the first data set.

12 . The method of claim 10 , further comprising:
retrieving the first data set from a memory area; and locally processing the first data set and the third data set at the processor module without transmitting data to or retrieving additional data from the memory area.

13 . The method of claim 10 , wherein processing a first data set comprises sequentially processing a plurality of elements included in the first data set.

14 . The method of claim 10 , wherein processing a first data set comprises processing a first element included in the first data set sequentially using a plurality of second elements included in the second data set.

15 . The method of claim 10 , wherein processing the third data set comprises generating, at one or more processor elements of the two-dimensional array, a respective output element per clock cycle.

16 . A mobile device comprising:
a sensor module configured to capture data corresponding to an image; a memory area storing computer-executable instructions for processing a first data set associated with the image; a first processor array configured to execute the computer-executable instructions to:
apply a first function to the first data set using a second data set to generate a third data set; and
apply a second function to the third data set to generate an output element, one or more processor elements of the first processor array configured to receive input from one or more first adjacent processor elements and transmit output to one or more second adjacent processor elements; and
a second processor array configured to execute the computer-executable instructions to aggregate the output element to at least partially generate a fourth data set.

17 . The mobile device of claim 16 , wherein the first processor array is configured to retrieve the first data set from a memory area, the first data set and the third data set processed locally at the mobile device without transmitting data to or retrieving additional data from the memory area.

18 . The mobile device of claim 16 , wherein the first processor array is arranged in a plurality of rows and a plurality of columns, one or more rows of the plurality of rows associated with a respective element of one or more first data sets, and one or more columns of the plurality of columns associated with a respective element of the second data set.

19 . The mobile device of claim 16 , wherein one or more processor elements of the first processor array are configured to sequentially process a plurality of elements included in the first data set.

20 . The mobile device of claim 16 , wherein one or more processor elements of the first processor array are configured to process a first element included in the first data set sequentially using a plurality of second elements included in the second data set.

Assignees

• Microsoft Technology Licensing Llc

Inventors

• Shoaib Mohammed
• Liu Jie
• Venkataramani Swagath

Classifications

• G06T1/20 Primary

  Processor architectures; Processor configuration, e.g. pipelining · CPC title

• G06F17/30592

  Physics · mapped topic

• G06F17/30292 Primary

  Physics · mapped topic

• G06F16/211 Primary

  Schema design and management · CPC title

• G06F16/283

  Multi-dimensional databases or data warehouses, e.g. MOLAP or ROLAP · CPC title