Multiple mode arithmetic circuit

Patent metadata

Field	Value
Publication number	US-12014150-B2
Application number	US-202318125190-A
Country	US
Kind code	B2
Filing date	Mar 23, 2023
Priority date	Aug 8, 2019
Publication date	Jun 18, 2024
Grant date	Jun 18, 2024

Abstract

A tile of an FPGA includes a multiple mode arithmetic circuit. The multiple mode arithmetic circuit is configured by control signals to operate in an integer mode, a floating-point mode, or both. In some example embodiments, multiple integer modes (e.g., unsigned, two's complement, and sign-magnitude) are selectable, multiple floating-point modes (e.g., 16-bit mantissa and 8-bit sign, 8-bit mantissa and 6-bit sign, and 6-bit mantissa and 6-bit sign) are supported, or any suitable combination thereof. The tile may also fuse a memory circuit with the arithmetic circuits. Connections directly between multiple instances of the tile are also available, allowing multiple tiles to be treated as larger memories or arithmetic circuits. By using these connections, referred to as cascade inputs and outputs, the input and output bandwidth of the arithmetic circuit is further increased.

First claim

What is claimed is:

1. A field programmable gate array (FPGA) comprising:
a mode selection input that selects a mode from a set of modes comprising a first mode and a second mode;
a plurality of integer arithmetic logic blocks; and
a plurality of output connections;
wherein:
in the first mode, the plurality of integer arithmetic logic blocks is configured to perform a real multiplication on first integer operands of a first size;
in the second mode, the plurality of integer arithmetic logic blocks is configured to perform a complex multiplication on second integer operands of a second size that is smaller than the first size; and
in the first mode and the second mode, the plurality of output connections provide a plurality of partial products, wherein a bit width of each partial product is based on a number of partial products provided.

2. The FPGA of claim 1 , wherein the second integer operands include at least two real values and two imaginary values.

3. The FPGA of claim 1 , further comprising:
a set of input connections; and
bit remapping circuitry that selectively connects the input connections to the integer arithmetic logic blocks based on the mode selection input, the bit remapping circuitry being operable in both the first mode and the second mode.

4. The FPGA of claim 3 , further comprising:
interconnection circuitry among the plurality of integer arithmetic logic blocks, the interconnection circuitry comprising a plurality of registers and multiplexers, the registers and multiplexers being operable in both the first mode and the second mode.

5. The FPGA of claim 1 , further comprising:
an adder that generates a result that is a sum of partial products.

6. The FPGA of claim 1 , wherein:
the first integer operands of the first size are sixteen-bit integers; and
the second integer operands of the second size are eight-bit integers.

7. The FPGA of claim 1 , wherein:
the first integer operands of the first size are thirty-two bit integers; and
the second integer operands of the second size are sixteen-bit integers.

8. A non-transitory machine-readable medium containing instructions that, when executed by one or more processors, cause the one or more processors to control configuration of a field programmable gate array (FPGA) comprising:
a mode selection input that selects a mode from a set of modes comprising a first mode and a second mode;
a plurality of integer arithmetic logic blocks; and
a plurality of output connections;
wherein:
in the first mode, the plurality of integer arithmetic logic blocks is configured to perform a real multiplication on first integer operands of a first size;
in the second mode, the plurality of integer arithmetic logic blocks is configured to perform a complex multiplication on second integer operands of a second size that is smaller than the first size; and
in the first mode and the second mode, the plurality of output connections provide a plurality of partial products, wherein a bit width of each partial product is based on a number of partial products provided.

9. The non-transitory machine-readable medium of claim 8 , wherein the second integer operands include at least two real values and two imaginary values.

10. The non-transitory machine-readable medium of claim 8 , wherein the FPGA further comprises:
a set of input connections; and
bit remapping circuitry that selectively connects the input connections to the integer arithmetic logic blocks based on the mode selection input, the bit remapping circuitry being operable in both the first mode and the second mode.

11. The non-transitory machine-readable medium of claim 10 , wherein the FPGA further comprises:
interconnection circuitry among the plurality of integer arithmetic logic blocks, the interconnection circuitry comprising a plurality of registers and multiplexers, the registers and multiplexers being operable in both the first mode and the second mode.

12. The non-transitory machine-readable medium of claim 8 , wherein the FPGA further comprises:
an adder that generates a result that is a sum of partial products.

13. The non-transitory machine-readable medium of claim 8 , wherein:
the first integer operands of the first size are sixteen-bit integers; and
the second integer operands of the second size are eight-bit integers.

14. A method comprising:
receiving, by a tile of a field programmable gate array (FPGA), a first mode selection input that selects a first mode from a set of modes comprising the first mode and a second mode;
in response to receiving the first mode selection input, configuring a plurality of integer arithmetic logic blocks to perform a real multiplication on first integer operands of a first size;
receiving, by the tile of the FPGA, a second mode selection input that selects the second mode from the set of modes;
in response to receiving the second mode selection input, configuring the plurality of integer arithmetic logic blocks to a complex multiplication on second integer operands of a second size that is smaller than the first size; and
providing, in the first mode and the second mode, by a plurality of output connections of the tile of the FPGA, a plurality of partial products, wherein a bit width of each partial product is based on a number of partial products provided.

15. The method of claim 14 , wherein the second integer operands include at least two real values and two imaginary values.

16. The method of claim 14 , further comprising:
selectively connecting, by the tile of the FPGA, input connections to the integer arithmetic logic blocks based on the first mode selection input and the second mode selection input.

17. The method of claim 16 , further comprising:
interconnecting, by the tile of the FPGA, the plurality of integer arithmetic logic blocks.

18. The method of claim 14 , further comprising:
generating, by an adder, a result that is a sum of partial products.

19. The method of claim 14 , wherein:
the first integer operands of the first size are sixteen-bit integers; and
the second integer operands of the second size are eight-bit integers.

20. The method of claim 14 , wherein:
the first integer operands of the first size are thirty-two bit integers; and
the second integer operands of the second size are sixteen-bit integers.

Assignees

• Achronix Semiconductor Corp

Inventors

• Pugh Daniel
• Nijssen Raymond
• Fitton Michael Philip
• Van Der Goot Marcel

Classifications

• G06F7/5443

  Sum of products (for applications thereof, see the relevant places, e.g. G06F17/10, H03H17/00) · CPC title

• G06F7/5324

  partitioned, i.e. using repetitively a smaller parallel parallel multiplier or using an array of such smaller multipliers · CPC title

• G06F2207/3824

  Accepting both fixed-point and floating-point numbers · CPC title

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title

• G06F7/4876 Primary

  Multiplying · CPC title