Display panel and display device

US12010886B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-12010886-B2
Application numberUS-202017295559-A
CountryUS
Kind codeB2
Filing dateJan 22, 2020
Priority dateJan 22, 2020
Publication dateJun 11, 2024
Grant dateJun 11, 2024

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

The present disclosure relates to the field of display, and discloses a display panel and a display device. The display panel includes: a base substrate including a first bonding region and a second bonding region; connection terminals located in the bonding regions and including first electric connecting structures and second electric connecting structures which are sequentially stacked, and particularly including first connection terminals and second connection terminals which are respectively located in the first bonding region and the second bonding region; a first insulating layer located between the first electric connecting structures and the second electric connecting structures, not overlapping the first connection terminals, and provided with first openings corresponding to the second connection terminals; and a second insulating layer located on one sides, facing away from the base substrate, of the second electric connecting structures, and provided with second openings corresponding to the connection terminals.

First claim

Opening claim text (preview).

What is claimed is: 1. A display panel, comprising: a base substrate, comprising a display region and a bonding region, wherein the bonding region is located on a side of the display region and is divided into a first bonding region and a second bonding region, wherein the first bonding region is located between the display region and the second bonding region; a plurality of connection terminals, located in the bonding region, wherein each connection terminal comprises a first electric connecting structure and a second electric connecting structure which are sequentially stacked on the base substrate, and the plurality of connection terminals comprise a plurality of first connection terminals located in the first bonding region and a plurality of second connection terminals located in the second bonding region; a first insulating layer disposed between a layer where the first electric connecting structure is located and a layer where the second electric connecting structure is located, wherein an orthographic projection of the first insulating layer on the base substrate does not overlap an orthographic projection of the first connection terminal on the base substrate, the first insulating layer overlaps the second bonding region and is provided with a plurality of first openings corresponding to the plurality of second connection terminals, an orthographic projection of each first opening on the base substrate is disposed within an orthographic projection of the first electric connecting structure of the corresponding second connection terminal on the base substrate, and the first electric connecting structure and the second electric connecting structure of each second connection terminal are connected through the corresponding first opening; and a second insulating layer disposed on a side, facing away from the base substrate, of the layer where the second electric connecting structure is located, wherein the second insulating layer overlaps the bonding region and is provided with a plurality of second openings corresponding to the plurality of connection terminals, and an orthographic projection of each second opening on the base substrate is disposed within an orthographic projection of the second electric connecting structure of the corresponding connection terminal on the base substrate. 2. The display panel according to claim 1 , wherein the first bonding region is a chip bonding region and the second bonding region is a flexible circuit board bonding region. 3. The display panel according to claim 1 , further comprising first lead wires disposed between the first connection terminals and the second connection terminals, wherein the first lead wires are disposed on the same layer as the second electric connecting structure; and the second electric connecting structures of the first connection terminals are connected with the second electric connecting structures of the second connection terminals through the first lead wires. 4. The display panel according to claim 1 , further comprising: a first layer of source and drain electrodes located in the display region and disposed between the base substrate and the first insulating layer, wherein the first electric connecting structures and the first layer of source and drain electrodes are prepared on the same layer; and a second layer of source and drain electrodes located in the display region and disposed between the first insulating layer and the second insulating layer, wherein the second electric connecting structures and the second layer of source and drain electrodes are prepared on the same layer; wherein the first insulating layer is a passivation layer, and the second insulating layer is a flat layer. 5. The display panel according to claim 4 , wherein the second insulating layer comprises a first thinned portion overlapping the first bonding region and a second thinned portion overlapping the second bonding region, wherein a thickness of the first thinned portion of the second insulating layer is smaller than a thickness of a portion surrounding the first thinned portion, and a thickness of the second thinned portion of the second insulating layer is smaller than a thickness of a portion surrounding the second thinned portion. 6. The display panel according to claim 5 , wherein the each connection terminal further comprises a third electric connecting structure disposed on the second opening of the second insulating layer, wherein the third electric connecting structure and the second electric connecting structure of the each connection terminal are connected through the second opening; and the display panel further comprises touch electrodes located in the display region and disposed on a side, facing away from the base substrate, of the second insulating layer, and the third electric connecting structures and the touch electrodes are prepared on the same layer. 7. The display panel according to claim 6 , wherein in the second bonding region, orthographic projections of the first electric connecting structure and the second electric connecting structure of each second connection terminal on the base substrate overlap, and the orthographic projections of the first openings on the base substrate overlap the orthographic projections of the second openings on the base substrate. 8. The display panel according to claim 6 , wherein an orthographic projection of the first electric connecting structure and an orthographic projection of the second electric connecting structure of the each connection terminal on the base substrate are disposed within an orthographic projection of the third electric connecting structure of the each connection terminal on the base substrate. 9. The display panel according to claim 6 , further comprising a pixel definition layer disposed between the second insulating layer and a layer where the touch electrodes are located, wherein the pixel definition layer is located within the display region. 10. The display panel according to claim 6 , further comprising an organic over coating disposed on a side, facing away from the base substrate, of a layer where the touch electrodes are located, wherein the organic over coating is provided with a third opening exposing the first bonding region and a fourth opening exposing the second bonding region; an orthographic projection of the first thinned portion on the base substrate is located in an orthographic projection of the third opening on the base substrate; and an orthographic projection of the fourth opening on the base substrate is located in an orthographic projection of the second thinned portion on the base substrate. 11. The display panel according to claim 4 , further comprising a third insulating layer disposed between the first insulating layer and a layer where the second layer of source and drain electrodes are located, wherein the third insulating layer is a flat layer disposed in the display region. 12. The display panel according to claim 4 , wherein the first electric connecting structures and the second electric connecting structures are a titanium/aluminum/titanium laminated structure. 13. A display device, comprising a display panel according to, wherein the display panel comprises: a base substrate, comprising a display region and a bonding region, wherein the bonding region is located on a side of the display region and is divided into a first bonding region and a second bonding region, wherein the first bonding region is located between the display region and the second bonding region; a plurality of connection terminals, located in the bonding region, wherein each connection terminal comprises a first elect

Assignees

Inventors

Classifications

  • Pixel-defining structures or layers, e.g. banks · CPC title

  • OLEDs integrated with touch screens · CPC title

  • G06F3/0412Primary

    Digitisers structurally integrated in a display · CPC title

  • Flexible OLED · CPC title

  • H10K59/131Primary

    Interconnections, e.g. wiring lines or terminals · CPC title

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What does patent US12010886B2 cover?
The present disclosure relates to the field of display, and discloses a display panel and a display device. The display panel includes: a base substrate including a first bonding region and a second bonding region; connection terminals located in the bonding regions and including first electric connecting structures and second electric connecting structures which are sequentially stacked, and p…
Who is the assignee on this patent?
Chengdu Boe Optoelect Tech Co, Boe Technology Group Co Ltd
What technology area does this patent fall under?
Primary CPC classification G06F3/0412. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Jun 11 2024 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 6 related publications on this page (citations in our corpus or others sharing the same primary CPC).