Semiconductor devices and methods of fabricating the same

Patent metadata

Field	Value
Publication number	US-12009398-B2
Application number	US-202217932851-A
Country	US
Kind code	B2
Filing date	Sep 16, 2022
Priority date	Jan 10, 2020
Publication date	Jun 11, 2024
Grant date	Jun 11, 2024

Abstract

A semiconductor device is disclosed. The semiconductor device includes a gate electrode on a substrate and extending in a first direction, source/drain patterns spaced apart from each other, in a second direction, with the gate electrode interposed therebetween, a gate contact electrically connected to the gate electrode, and an active contact electrically connected to at least one of the source/drain patterns. The active contact includes a lower contact pattern electrically connected to the at least one of the source/drain patterns, the lower contact pattern having a first width in the first direction, and an upper contact pattern electrically connected to a top surface of the lower contact pattern, the upper contact pattern having a second width in the first direction that is smaller than the first width. The upper contact pattern and the gate contact horizontally overlap each other.

First claim

What is claimed is:

1. A method of fabricating a semiconductor device, the method comprising
forming a first active pattern on a substrate;
forming a source/drain pattern on the first active pattern;
forming a gate electrode on the first active pattern;
forming an interlayer insulating layer on the gate electrode and the source/drain pattern;
forming a contact hole to penetrate the interlayer insulating layer and to expose the source/drain pattern;
forming a lower contact pattern in a lower portion of the contact hole;
forming a sacrificial layer on the lower contact pattern in the contact hole;
removing a portion of the sacrificial layer to form a sacrificial pattern including a first opening;
forming a mold pattern in the first opening; and
replacing the sacrificial pattern with an upper contact pattern.

2. The method of claim 1 , wherein the first opening is formed to expose a top surface of the lower contact pattern.

3. The method of claim 1 , wherein the replacing of the sacrificial pattern with the upper contact pattern comprises:
selectively etching the sacrificial pattern in the contact hole to form a second opening; and
forming a conductive layer in the second opening.

4. The method of claim 1 , wherein the forming of the lower contact pattern in the lower portion of the contact hole comprises:
forming a preliminary contact pattern in the contact hole; and
removing an upper portion of the preliminary contact pattern.

5. The method of claim 1 , wherein the sacrificial pattern comprises an amorphous carbon layer.

6. The method of claim 1 , wherein replacing the sacrificial pattern with the upper contact pattern comprises:
forming a second barrier pattern; and
forming a second conductive pattern on the second barrier pattern.

7. The method of claim 6 , wherein the second barrier pattern contacts the lower contact pattern.

8. The method of claim 6 , wherein the lower contact pattern comprises a first conductive pattern and a first barrier pattern that is on side and bottom surfaces of the first conductive pattern.

9. The method of claim 8 , wherein a thickness of the second barrier pattern is different from a thickness of the first barrier pattern.

10. The method of claim 1 , wherein the mold pattern includes silicon oxide, silicon nitride, or silicon oxynitride.

11. The method of claim 1 , further comprising forming a gate contact on the gate electrode,
wherein the upper contact pattern and the gate contact horizontally overlap each other.

12. The method of claim 11 , wherein the gate contact is formed through a separate process from that for the upper contact pattern.

13. The method of claim 11 , further comprising:
forming a first via on the upper contact pattern; and
forming a second via on the gate contact,
wherein the first via and the second via horizontally overlap each other.

14. A method of fabricating a semiconductor device, the method comprising
forming a first active pattern on a substrate;
forming a source/drain pattern on the first active pattern;
forming a gate electrode on the first active pattern;
forming an interlayer insulating layer on the gate electrode and the source/drain pattern;
forming a contact hole to penetrate the interlayer insulating layer and to expose the source/drain pattern;
forming a lower contact pattern in a lower portion of the contact hole;
forming a sacrificial pattern on the lower contact pattern in the contact hole;
replacing the sacrificial pattern with an upper contact pattern; and
forming a gate contact on the gate electrode,
wherein the upper contact pattern and the gate contact horizontally overlap each other.

15. The method of claim 14 , wherein replacing the sacrificial pattern with the upper contact pattern comprises:
forming a second barrier pattern; and
forming a second conductive pattern on the second barrier pattern.

16. The method of claim 15 , wherein the second barrier pattern contacts the lower contact pattern.

17. The method of claim 15 , wherein the lower contact pattern comprises a first conductive pattern and a first barrier pattern that is on side and bottom surfaces of the first conductive pattern.

18. The method of claim 17 , wherein a thickness of the second barrier pattern is different from a thickness of the first barrier pattern.

19. The method of claim 14 , wherein the gate contact is formed through a separate process from that for the upper contact pattern.

20. The method of claim 14 , further comprising:
forming a first via on the upper contact pattern; and
forming a second via on the gate contact,
wherein the first via and the second via horizontally overlap each other.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Song Hyun-Seung
• Kim Tae-Yeol
• Baek Jae-Jik

Classifications

• H10W20/0693

  by forming self-aligned vias · CPC title

• H10W20/0696

  by using sacrificial placeholders, e.g. using sacrificial plugs · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title

• H10W20/033

  in openings in dielectrics · CPC title