Fabricating wafers with electrical contacts on a surface parallel to an active surface

Patent metadata

Field	Value
Publication number	US-12009352-B2
Application number	US-202017419385-A
Country	US
Kind code	B2
Filing date	Sep 16, 2020
Priority date	Sep 26, 2019
Publication date	Jun 11, 2024
Grant date	Jun 11, 2024

Abstract

Provided herein include various examples of a method for manufacturing aspects of an apparatus, a sensor system. The method may include obtaining a first carrier bonded to an upper surface of the silicon wafer. This wafer includes through silicon vias (TSVs) extended through openings in a passivation stack, with electrical contacts coupled to portions of the TSVs exposed through these openings. The method may include de-bonding the first carrier from the upper surface of the silicon wafer. The method may include dicing the silicon wafer into subsections comprising dies.

First claim

What is claimed is:

1. A method comprising:
obtaining a first carrier bonded to an upper surface of the silicon wafer, wherein one or more through silicon vias are extended through the silicon wafer and a passivation stack, wherein the passivation stack is disposed below a bottom surface of the silicon wafer, wherein a portion of each of the one or more through silicon vias is exposed through an opening of one or more openings in the passivation stack, wherein each exposed portion is coupled to one or more electrical contacts;
de-bonding the first carrier from the upper surface of the silicon wafer; and
dicing the silicon wafer into subsections comprising dies, such that each die comprises a portion of the upper surface of the silicon wafer, the portion of the upper surface of the silicon wafer comprising an active surface, at least one through silicon via of the one or more through silicon vias, and at least one electrical contact of the one or more electrical contacts on a second surface of the die, the second surface of the die parallel to the active surface.

2. The method of claim 1 , further comprising:
forming fan-out regions, the forming comprising:
coupling the active surfaces of the dies to a fan-out carrier, the coupling creating a first space adjacent to a first edge of each active surface of each die and a second space adjacent to a second edge of each active surface of each die;
forming a molding layer by depositing mold on the second surfaces of the dies and in each first space and each second space to form the molding layer over the fan-out carrier; and
polishing a top surface of the molding layer such that the at least one electrical contact of the one or more electrical contacts on the second surface of each die and the polished top surface of the molding layer form a contiguous surface.

3. The method of claim 2 , wherein the contiguous surface comprises flat electrical contacts of equal height and thickness.

4. The method of claim 2 , further comprising:
forming a metallization layer by coating metal on the contiguous surface in a pattern.

5. The method of claim 4 , wherein the metallization layer comprises a layer selected from the group consisting of: a fan-out redistribution layer based on the pattern distributing additional electrical contacts at locations different from locations of the at least one electrical contact of the one or more electrical contacts on the second surface of each die, and an under bump layer, based on the pattern distributing additional electrical contacts at locations of the at least one electrical contact of the one or more electrical contacts on the second surface of each die.

6. The method of claim 4 , wherein coating the metal on the contiguous surface comprises:
utilizing a photolithography technique to create the pattern;
electroplating the pattern, wherein the electroplating comprises depositing on the one or more openings, wherein the one or more openings comprise photoresist; and
stripping away the photoresist to reveal the metallization layer.

7. The method of claim 4 , further comprising:
depositing an electrical short prevention passivation layer on the metallization layer; and
utilizing photolithography to open the electrical short prevention passivation layer at one or more locations to from electrical connection pads to the metallization layer.

8. The method of claim 7 , further comprising, releasing the fan-out carrier to expose an active device surface comprising the active surfaces of the dies and surfaces of the first spaces and the second spaces contiguous with the active surfaces, the releasing comprising:
attaching a second carrier to the electrical short prevention passivation layer with an adhesive material; and
de-coupling the fan-out carrier from the active surfaces of the dies utilizing a technique selected from the group consisting of: applying mechanical pressure, heating the fan-out carrier, and applying a solvent.

9. The method of claim 7 , further comprising:
preparing the active device surface to act as a sensor, the preparing comprising:
washing the active device surface; and
processing the active device surface.

10. The method of claim 9 , further comprising:
forming a fluidic flow channel over the active device surface, comprising:
attaching one or more lids to a portion of the mold to form the fluidic flow channel between the active device surface and the one or more lids; and
removing the second carrier from the electrical short prevention passivation layer to create a resultant structure.

11. The method of claim 10 , further comprising:
dicing the resultant structure into sub-structures, wherein each substructure comprises at least one die and at least one lid.

12. The method of claim 2 , further comprising:
forming a new passivation layer on the contiguous surface to planarize the contiguous surface;
forming openings in the new passivation layer to expose the at least one electrical contact of the one or more electrical contacts on the second surface of each die; and
forming a metallization layer by coating metal on the new passivation layer in a pattern.

13. The method of claim 2 , wherein coupling the active surfaces of the dies to the fan-out carrier comprises forming a temporary bonding layer between the active surfaces and the fan-out carrier, wherein the temporary bonding layer protects the active surfaces during the forming of the fan-out regions.

14. The method of claim 2 , wherein forming the molding layer further comprises curing the mold to attain mechanical stability, and wherein the molding layer is deposited to reach a height greater than a height of the at least one electrical contact on the second surface of each die.

15. The method of claim 1 , wherein the passivation stack comprises a metallization layer.

16. The method of claim 15 , wherein the metallization layer comprises a redistribution layer.

17. The method of claim 1 , wherein the obtaining comprises fabricating the one or more electrical contacts on the one or more openings in the passivation stack.

18. The method of claim 1 , further comprising:
prior to dicing the silicon wafer into subsections, placing the silicon wafer on a second carrier, such that the second carrier is coupled to the passivation stack;
prior to forming fan-out regions, releasing the second carrier from the silicon wafer.

19. A method comprising:
obtaining a first carrier bonded to an upper surface of the silicon wafer, wherein one or more through silicon vias are extended through the silicon wafer and a passivation stack, wherein the passivation stack is disposed below a bottom surface of the silicon wafer, wherein a portion of each of the one or more through silicon vias is exposed through an opening of one or more openings in the passivation stack;
fabricating one or more pillar bumps on the openings in the passivation stack;
de-bonding the first carrier from the upper surface of the silicon wafer; and
dicing the silicon wafer into subsections comprising dies.

20. A method comprising:
obtaining a first carrier bonded to an upper surface of the silicon wafer, wherein one or more through silicon vias are extended through the silicon wafer and a passivation stack, wherein the passivation stack is disposed below a bottom surface of the silicon wafer, wherein a portion of each of the one or more through silicon vias is exposed through an opening of one or more openings in the passivation stack, wherein one or more electrical contacts are

Assignees

• Illumina Inc

Inventors

• Emadi Arvin
• Aday Jon
• Agah Ali
• Rival Arnaud

Classifications

• H10W70/652

  Cross-sectional shapes · CPC title

• H10W70/655

  Fan-out layouts · CPC title

• H10W70/60

  Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) · CPC title

• H10W72/221

  Structures or relative sizes · CPC title

• H10W72/01212

  at a different location than on the final device, e.g. forming as prepeg · CPC title