Semiconductor package structure and method for manufacturing the same

Patent metadata

Field	Value
Publication number	US-12009317-B2
Application number	US-202117321139-A
Country	US
Kind code	B2
Filing date	May 14, 2021
Priority date	May 14, 2021
Publication date	Jun 11, 2024
Grant date	Jun 11, 2024

Abstract

A semiconductor package structure and a method for manufacturing a semiconductor package structure are provided. The semiconductor package structure includes a substrate, a semiconductor device, an encapsulant, a balance structure, and a warpage-resistant layer. The semiconductor device is disposed on the substrate. The encapsulant encapsulates the semiconductor device. The balance structure is on the semiconductor device and contacting the encapsulant. The warpage-resistant layer is between the semiconductor device and the balance structure. The encapsulant contacts a lateral surface of the warpage-resistant layer.

First claim

What is claimed is:

1. A semiconductor package structure, comprising:
a substrate;
a semiconductor device disposed over the substrate;
an encapsulant encapsulating the semiconductor device;
a balance structure over the semiconductor device and contacting the encapsulant; and
a warpage-resistant layer between the semiconductor device and the balance structure, wherein the warpage-resistance layer comprises a metal layer,
wherein the balance structure comprises a metal material directly contacting the warpage-resistant layer; and
wherein the warpage-resistant layer comprises a microstructure on a surface contacting the balance structure.

2. The semiconductor package structure as claimed in claim 1 , wherein the warpage-resistant layer comprises titanium/copper.

3. The semiconductor package structure as claimed in claim 1 , wherein the balance structure is entirely above the warpage-resistant layer.

4. The semiconductor package structure as claimed in claim 3 , wherein a lateral surface of the balance structure substantially aligns to a lateral surface of the warpage-resistance layer and a lateral surface of the semiconductor device.

5. The semiconductor package structure as claimed in claim 1 , wherein a bottommost surface of the balance structure directly contacts a topmost surface of the warpage-resistant layer.

6. The semiconductor package structure as claimed in claim 1 , wherein the balance structure is entirely above the warpage-resistant layer, and a bottommost surface of the balance structure directly contacts a topmost surface of the warpage-resistant layer.

7. The semiconductor package structure as claimed in claim 1 , wherein a peripheral outline of the balance structure overlaps a peripheral outline of the substrate from a top view perspective.

8. A semiconductor package structure, comprising:
a substrate;
a semiconductor device disposed over the substrate;
an encapsulant encapsulating the semiconductor device;
a balance structure over the semiconductor device and contacting the encapsulant; and
a warpage-resistant layer between the semiconductor device and the balance structure, wherein the warpage-resistance layer comprises a metal layer,
wherein a surface roughness of an upper surface of the balance structure is greater than a surface roughness of a bottom surface of the balance structure.

9. A semiconductor package structure, comprising:
a substrate;
a semiconductor device disposed over the substrate;
an encapsulant encapsulating the semiconductor device;
a balance structure over the semiconductor device and contacting the encapsulant; and
a warpage-resistant layer between the semiconductor device and the balance structure, wherein the warpage-resistance layer comprises a metal layer,
wherein a surface roughness of an upper surface of the warpage-resistant layer is greater than a surface roughness of a bottom surface of the warpage-resistant layer.

Assignees

• Advanced Semiconductor Eng

Inventors

• Yen You-Lung
• Appelt Bernd Karl
• Essig Kay Stefan

Classifications

• H10W74/111

  the semiconductor body being completely enclosed · CPC title

• H10W74/01

  Manufacture or treatment · CPC title

• H10W70/424

  Cross-sectional shapes (H10W70/481 takes precedence) · CPC title

• H10W40/77

  Auxiliary members characterised by their shape · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title