Heterogeneous integration of components onto compact devices using moiré based metrology and vacuum based pick-and-place

Patent metadata

Field	Value
Publication number	US-12009247-B2
Application number	US-202217959932-A
Country	US
Kind code	B2
Filing date	Oct 4, 2022
Priority date	Dec 23, 2016
Publication date	Jun 11, 2024
Grant date	Jun 11, 2024

Abstract

A method for assembling heterogeneous components. The assembly process includes using a vacuum based pickup mechanism in conjunction with sub-nm precise moiré alignment techniques resulting in highly accurate, parallel assembly of feedstocks.

First claim

The invention claimed is:

1. A method for assembling components onto a product substrate, the method comprising:
selectively picking one or more elements from a source wafer by a vacuum superstrate attached to said one or more elements;
placing said selectively picked one or more elements onto an adhesive on said product substrate with sub-100 nm placement precision, wherein said adhesive is in a liquid state at a time of said placing which enables said sub-100 nm placement precision, wherein said adhesive is inkjetted or spin-coated onto said product substrate; and
securely attaching said selectively picked one or more elements onto said product substrate by holding onto said one or more elements using said vacuum superstrate until said adhesive reaches its gel point.

2. The method as recited in claim 1 , wherein said placement of said selectively picked one or more elements onto said adhesive on said product substrate is arbitrary.

3. The method as recited in claim 1 , wherein said selectively picking and said placing are performed in a massively parallel manner.

4. The method as recited in claim 1 , wherein said one or more elements are fabricated on source wafers with a buried sacrificial layer that is partially or fully removed using a bulk etch process.

5. The method as recited in claim 4 further comprising:
etching said buried sacrificial layer using an etchant, wherein said etchant comprises vapor hydrofluoric acid.

6. The method as recited in claim 5 , wherein said etching of said buried sacrificial layer using said etchant is timed in such a manner that pillar-like structures remain underneath said one or more elements post-etch.

7. The method as recited in claim 4 further comprising:
bulk-releasing said one or more elements by etching off an underlying sacrificial layer while holding a vacuum.

8. The method as recited in claim 7 further comprising:
transferring said one or more elements to an intermediate glass substrate with an ultraviolet-de-tacking adhesive on said intermediate glass substrate.

9. The method as recited in claim 8 further comprising:
exposing an underside of an element of said one or more elements to selective ultraviolet light to selectively release said element.

10. The method as recited in claim 1 , wherein said one or more elements from said source wafer have access holes to an underlying sacrificial layer.

11. The method as recited in claim 1 , wherein alignment between said vacuum superstrate and said product substrate is achieved using a moiré metrology scheme.

12. The method as recited in claim 1 further comprising:
performing coarse alignment using stage actuators as said selectively picked one or more elements are brought to said product substrate; and
performing fine alignment after said one or more elements are touching said adhesive on said product substrate in an uncured state.

13. The method as recited in claim 1 , wherein said one or more elements are encapsulated in a chemically inert layer of a particular thickness to protect from chemical damage due to a subsequent material removal process and to mitigate mechanical scratching.

14. The method as recited in claim 13 , wherein said chemically inert layer comprises aluminum oxide or amorphous carbon.

15. The method as recited in claim 1 further comprising:
selectively attaching to said one or more elements using a vacuum based pickup mechanism; and
selectively releasing said one or more elements using an etchant gas or a mechanical pulling approach.

16. The method as recited in claim 1 , wherein said adhesive is cured using ultraviolet light until it reaches said gel point.

17. The method as recited in claim 1 , wherein, once said product substrate has been fully populated with elements, one or more of a material deposition and a coating is performed, followed by a planarization.

18. The method as recited in claim 17 , wherein said planarization utilizes one or more of the following: an inkjet-based planarization and a chemical mechanical polishing.

19. The method as recited in claim 1 , wherein said one or more elements are selectively picked from said source wafer using vacuum-based pickup, wherein valves are used to activate vacuum holes on said vacuum superstrate to enable said vacuum-based pickup.

20. The method as recited in claim 19 , wherein said activation of said vacuum holes is performed in an addressable manner.

21. The method as recited in claim 19 , wherein said vacuum holes are arranged in substantially a same lattice as said product substrate in its final form.

22. The method as recited in claim 1 , wherein a top surface of said one or more elements placed onto said adhesive on said product substrate is at a same height or higher than all previously placed elements on said product substrate.

23. The method as recited in claim 1 , wherein a thickness of said adhesive is varied by using pre-calculated volumes of adhesive drops.

24. The method as recited in claim 1 , wherein said adhesive shrinks by 2-10% by volume upon reaching said gel point.

25. A method for assembling components onto a product substrate, the method comprising:
selectively picking one or more elements from a source wafer by a vacuum superstrate attached to said one or more elements;
placing said selectively picked one or more elements onto said product substrate, wherein said placing is performed with sub-100 nm placement precision; and
securely attaching said selectively picked one or more elements onto said product substrate using direct bonding by holding onto said one or more elements using said vacuum superstrate until said attachment occurs.

26. The method as recited in claim 25 , wherein alignment between said vacuum superstrate and said product substrate is achieved using a moiré metrology scheme.

27. The method as recited in claim 25 , wherein a top surface of said one or more elements placed onto said product substrate is at a same height or higher than all previously placed elements on said product substrate.

28. The method as recited in claim 25 , wherein, once said product substrate has been fully populated with elements, one or more of a material deposition and a coating is performed, followed by a planarization.

29. The method as recited in claim 28 , wherein said planarization utilizes one or more of the following: an inkjet-based planarization and a chemical mechanical polishing.

30. A method for assembling components onto a product substrate, the method comprising:
selectively picking one or more elements from a source wafer by a vacuum superstrate attached to said one or more elements;
placing said selectively picked one or more elements onto an adhesive on said product substrate, wherein a top surface of said one or more elements being placed onto said adhesive on said product substrate is at a same height or higher than all previously placed elements on said product substrate, wherein said adhesive is in a liquid state at a time of said placing, wherein said adhesive is inkjetted or spin-coated onto said product substrate; and
securely attaching said selectively picked one or more elements onto said product substrate by holding onto said one or more elements using said vacuum superstrate until said adhesive reaches its gel point.

31. The method as recited in claim 30 , whe

Assignees

• Univ Texas

Inventors

• Sreenivasan Sidlgata V
• Ajay Paras
• Sayal Aseem
• Mcdermott Mark
• Singhal Shrawan
• Abed Ovadia
• Dunn Lawrence
• Goyal Vipul
• Cullinan Michael

Classifications

• H10P72/7434

  used in a transfer process involving at least two transfer steps, i.e. including an intermediate handle substrate · CPC title

• H10P72/7428

  used to support diced chips prior to mounting · CPC title

• H10P72/7414

  the auxiliary support including means facilitating the selective separation of some of a plurality of devices from the auxiliary support · CPC title

• H10P72/7408

  the auxiliary support including alignment aids · CPC title

• H10P72/744

  Details of chemical or physical process used for separating the auxiliary support from a device or a wafer · CPC title