Receiver, operation method thereof, and memory device
US-2024412764-A1 · Dec 12, 2024 · US
Semiconductor integrated circuit
US2016141014A1 · US · A1
| Field | Value |
|---|---|
| Publication number | US-2016141014-A1 |
| Application number | US-201615004060-A |
| Country | US |
| Kind code | A1 |
| Filing date | Jan 22, 2016 |
| Priority date | Jun 29, 2012 |
| Publication date | May 19, 2016 |
| Grant date | — |
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Abstract
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A semiconductor integrated circuit including first semiconductor chip and second semiconductor chip that are vertically stacked, wherein the first semiconductor chip includes a first column data driving circuit configured to transmit internal data to the second semiconductor chip in a DDR (double data rate) scheme based on an internal strobe signal, and a first column strobe signal driving circuit configured to generate first column strobe signals that are source-synchronized with first column data transmitted to the second semiconductor chip by the first column data driving circuit, based on the internal strobe signal, and transmit the first column strobe signals to the second semiconductor chip.
First claim
Opening claim text (preview).
1 - 16 . (canceled) 17 . A semiconductor integrated circuit including at least one master chip and at least one slave chip that are stacked, the master chip being configured to transmit write data inputted from an outside, to the slave chip in a DDR scheme based on a first internal strobe signal, transmit write strobe signals that are source-synchronized with the write data transmitted in the DDR scheme, to the slave chip based on the first internal strobe signal, and rece…
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Physics · mapped topic
- G11C7/222Primary
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
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- What does patent US2016141014A1 cover?
- A semiconductor integrated circuit including first semiconductor chip and second semiconductor chip that are vertically stacked, wherein the first semiconductor chip includes a first column data driving circuit configured to transmit internal data to the second semiconductor chip in a DDR (double data rate) scheme based on an internal strobe signal, and a first column strobe signal driving circ…
- Who is the assignee on this patent?
- Sk Hynix Inc
- What technology area does this patent fall under?
- Primary CPC classification G11C7/222. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Thu May 19 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).