Flexible resource assignment to physical and virtual functions in a virtualized processing system

Patent metadata

Field	Value
Publication number	US-12008389-B2
Application number	US-201816189119-A
Country	US
Kind code	B2
Filing date	Nov 13, 2018
Priority date	Nov 13, 2018
Publication date	Jun 11, 2024
Grant date	Jun 11, 2024

Abstract

A method and system for flexibly assigning hardware resources to physical and virtual functions in a processor system supporting hardware virtualization is disclosed. The processor system includes a resource virtualization unit which is used to flexibly assign hardware resources to physical functions and also flexibly assign local functions to virtual functions associated with one or more of the physical functions. Thereby, standard PCI software is compatible with the physical functions and any associated virtualized hardware resources that have been flexibly assigned to the virtual and local functions.

First claim

What is claimed is:

1. A method in a processing system for programming physical functions and virtual functions, the method comprising:
defining a plurality of virtual functions, wherein each of the virtual functions of the plurality of virtual functions comprises a range of local functions;
defining a plurality of physical functions comprising one or more physical functions;
programming a set of the plurality of virtual functions to correspond to a first physical function of the plurality of physical functions;
defining a plurality of hardware resources corresponding to one or more functional blocks, wherein each of the local functions of the range of local functions is assigned a set of the plurality of hardware resources; and
programming at least one hardware resource of the plurality of hardware resources to be assigned to one or more of: the first physical function and a first virtual function of the set of the plurality of virtual functions,
wherein the range of local functions comprises a first local function in a source socket, wherein the first local function is associated with a first functional block of the one or more functional blocks,
wherein the first local function communicates with a second local function in a destination socket using a combination uniquely identifying one of a physical function and a virtual function corresponding to the second local function, and
wherein the second local function is assigned from the first functional block.

2. The method of claim 1 , wherein the processing system comprises more than one hardware resource and more than one physical function.

3. The method of claim 1 , wherein the one or more physical functions follow a PCIe standard, and an administrative function's registers are accessed through PCIe BAR regions of the one or more physical functions.

4. The method of claim 3 , wherein software selects the one or more physical functions to access the administrative function's registers.

5. The method of claim 1 , wherein DMA operations executed for a hardware resource of the at least one hardware resource use at least one of:
address translation tables of the first physical function; and
address translation tables of a designated physical function of the one or more physical functions.

6. The method of claim 1 , further comprising assigning one or more administrative functions by software to at least one physical function of the one or more physical functions.

7. The method of claim 1 , wherein registers of a hardware resource of the at least one hardware resource are accessed through a physical address range selected from: a physical address range of the first physical function and a physical address range region of the first virtual function.

8. The method of claim 7 , wherein:
a first subset of address bits in the selected physical address range identify a functional block of the one or more functional blocks which provides the hardware resource; and
a second subset of address bits in the selected physical address range region identify an address slot assigned to the hardware resource.

9. The method of claim 1 , further comprising assigning interrupts from the one or more functional blocks to different PCIe MSI-X interrupt vectors belonging to at least one of: the plurality of virtual functions and the one or more physical functions.

10. The method of claim 1 , wherein programming the set of the plurality of virtual functions comprises:
defining one or more ranges of consecutive virtual functions; and
assigning each range of the consecutive virtual functions to one physical function.

11. The method of claim 1 , wherein the plurality of hardware resources is associated with the one or more functional blocks, the one or more functional blocks comprising one or more of:
a network interface controller;
a network pool allocator unit;
a schedule, synchronize, and order unit;
a timers unit;
a cryptographic accelerator unit;
a compression/decompression engine;
an expression matching engine; and
a RAID accelerator unit.

12. The method of claim 1 , wherein the local functions comprise at least one of: instruction queues, packet queues, work queues, timer rings, and memory pools.

13. The method of claim 1 , further comprising:
determining a number of the physical functions required by a software application;
determining a number of the virtual functions per physical function of the number of the physical functions; and
assigning the plurality of hardware resources to each virtual function of the number of the virtual functions.

14. The method of claim 13 , wherein:
said programming the set of the plurality of virtual functions comprises mapping a range of virtual functions of the plurality of virtual functions to the first physical function; and
said programming at least one hardware resource comprises mapping a range of hardware virtual functions to the first physical function and thereby to the range of virtual functions.

15. The method of claim 1 , wherein the combination comprises a unique combination of a physical function number and a function number and has a unique physical address range.

16. A semiconductor device, comprising:
a plurality of hardware resources operable for processing data and corresponding to one or more functional blocks;
a resource virtualization unit coupled to the plurality of hardware resources and operable for assigning a plurality of virtual functions to a plurality of physical functions comprising one or more physical functions and for assigning the plurality of hardware resources to a first physical function of the plurality of physical functions and a first virtual function of the plurality of virtual functions, wherein each of the virtual functions of the plurality of virtual functions comprises a range of local functions and each of the local functions of the range of local functions is assigned a set of the plurality of hardware resources; and
a plurality of processors coupled to the resource virtualization unit and operable for processing the data by the first physical function and the first virtual function utilizing the plurality of hardware resources,
wherein the range of local functions comprises a first local function in a source socket, wherein the first local function is associated with a first functional block of the one or more functional blocks,
wherein the first local function communicates with a second local function in a destination socket using a combination uniquely identifying one of a physical function and a virtual function corresponding to the second local function, and
wherein the second local function is assigned from the first functional block.

17. The semiconductor device of claim 16 , wherein interrupts from one or more functional blocks associated with the plurality of hardware resources are assigned to different PCIe MSI-X interrupt vectors belonging to the plurality of virtual functions and the one or more physical functions.

18. The semiconductor device of claim 16 , wherein the one or more functional blocks comprise at least one of:
a network interface controller;
a network pool allocator unit;
a schedule, synchronize, and order unit;
a timers unit;
a cryptographic accelerator unit;
a compression/decompression engine;
an expression matching engine; and
a RAID accelerator unit.

19. The semiconductor device of claim 18 , further comprising a memory coupled to the plurality of processors, wherein the memory stores administrative software that assigns the plurality of

Assignees

• Cavium Llc
• Marvell Asia Pte Ltd

Inventors

• Krakirian Shahe
• Zebchuk Jason
• Snyder Ii Wilson Parkhurst

Classifications

• G06F13/28

  using burst mode transfer, e.g. direct memory access {DMA}, cycle steal (G06F13/32 takes precedence) · CPC title

• G06F2009/45579

  I/O management, e.g. providing access to device drivers or storage · CPC title

• G06F13/24 Primary

  using interrupt (G06F13/32 takes precedence) · CPC title

• G06F2213/0026

  PCI express · CPC title

• G06F13/4282

  on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247) · CPC title