Power efficient memory value updates for arm architectures

Patent metadata

Field	Value
Publication number	US-12007936-B2
Application number	US-202217580866-A
Country	US
Kind code	B2
Filing date	Jan 21, 2022
Priority date	Jan 21, 2022
Publication date	Jun 11, 2024
Grant date	Jun 11, 2024

Abstract

Disclosed are various examples of providing provide efficient waiting for detection of memory value updates for Advanced RISC Machines (ARM) architectures. An ARM processor component instructs a memory agent to perform a processing action, and executes a waiting function. The waiting function ensures that the processing action is completed by the memory agent. The waiting function performs an exclusive load at a memory location, and a wait for event (WFE) instruction that causes the ARM processor component to wait in a low-power mode for an event register to be set. Once the event register is set, the waiting function completes and a second processing action is executed by the ARM processor component.

First claim

Therefore, the following is claimed:

1. A non-transitory computer-readable medium comprising executable instructions, wherein the instructions, when executed by at least one processor, cause the at least one processor to at least:
execute, by an Advanced RISC Machines (ARM) processor component, a first processing action;
transmit, by the ARM processor component, at least one command to a memory agent, the at least one command comprising instructions to perform a second processing action;
execute, by the ARM processor component, a waiting function to ensure that the second processing action is completed by the memory agent prior to a third processing action, the waiting function comprising: an exclusive load implemented using an LDXR instruction at a memory location, and a wait for event implemented using a WFE instruction that causes the ARM processor component to wait in a low-power mode for an event register to be set, followed by a data barrier implemented using a DMB instruction or a DSB instruction, wherein an NSHLD option specified as instructions for the data barrier causes execution of the data barrier to provide an ordering operation that waits only for loads to complete and only out to a point of unification, thereby ensuring that the LDXR instruction and the WFE instruction are executed prior to other instructions of the waiting function, and wherein the waiting function completes the other instructions based at least in part on the event register becoming set, wherein the other instructions confirm that the event register is set by the second processing action rather than a false positive event; and
execute, by the ARM processor component, the third processing action based at least in part on completion of the waiting function.

2. The non-transitory computer-readable medium of claim 1 , wherein the first processing action, the second processing action, and the third processing action are an ordered set of actions of a workload.

3. The non-transitory computer-readable medium of claim 1 , wherein the ARM processor component comprises a central processing unit, a core, or a thread.

4. The non-transitory computer-readable medium of claim 1 , wherein the memory agent comprises one of: the ARM processor component, an x86 processor component, or a device comprising a memory writing capability.

5. The non-transitory computer-readable medium of claim 4 , wherein the event register becoming set provides an unverified indication that the second processing action is completed by the memory agent.

6. The non-transitory computer-readable medium of claim 1 , wherein the at least one command specifies a pointer to the memory location.

7. The non-transitory computer-readable medium of claim 1 , wherein the waiting function evaluates a condition that compares a value at the memory location to a predetermined value to verify that the second processing action is completed.

8. A system, comprising:
at least one computing device comprising at least one processor; and
a data store comprising executable instructions, wherein the instructions, when executed by the at least one processor, cause the at least one computing device to at least:
transmit, by an Advanced RISC Machines (ARM) processor component, at least one command to a memory agent, the at least one command comprising instructions to perform a first processing action;
execute, by the ARM processor component, a waiting function to ensure that the first processing action is completed by the memory agent prior to a second processing action, the waiting function comprising: an exclusive load implemented using an LDXR instruction at a memory location, and a wait for event implemented using a WFE instruction that causes the ARM processor component to wait in a low-power mode for an event register to be set, followed by a data barrier implemented using a DMB instruction or a DSB instruction, wherein an option specified as instructions for the data barrier causes execution of the data barrier to provide an ordering operation that waits only for loads to complete and only out to a point of unification, thereby ensuring that the LDXR instruction and the WFE instruction are executed prior to other instructions of the waiting function, and wherein the waiting function completes the other instructions based at least in part on the event register becoming set, wherein the other instructions confirm that the event register is set by the first processing action rather than a false positive event; and
execute, by the ARM processor component, a second processing action based at least in part on completion of the waiting function.

9. The system of claim 8 , wherein the first processing action and the second processing action are an ordered set of actions of a workload.

10. The system of claim 8 , wherein the ARM processor component comprises a central processing unit, a core, or a thread.

11. The system of claim 8 , wherein the memory agent comprises one of: the ARM processor component, an x86 processor component, or a device comprising a memory writing capability.

12. The system of claim 11 , wherein the event register becoming set provides an unverified indication that the first processing action is completed by the memory agent.

13. The system of claim 8 , wherein the at least one command specifies a pointer to the memory location.

14. The system of claim 8 , wherein the waiting function evaluates a condition that compares a value at the memory location to a predetermined value to verify that the first processing action is completed.

15. A method, comprising:
transmitting, by an Advanced RISC Machines (ARM) processor component, at least one command to a memory agent, the at least one command comprising instructions to perform a first processing action;
executing, by the ARM processor component, a waiting function to ensure that the first processing action is completed by the memory agent prior to a second processing action, the waiting function comprising: an exclusive load implemented using an LDXR instruction at a memory location, and a wait for event implemented using a WFE instruction that causes the ARM processor component to wait in a low-power mode for an event register to be set, followed by a data barrier implemented using a DMB instruction or a DSB instruction, wherein an option specified as instructions for the data barrier causes execution of the data barrier to provide an ordering operation that waits only for loads to complete and only out to a point of unification, thereby ensuring that the LDXR instruction and the WFE instruction are executed prior to other instructions of the waiting function, and wherein the waiting function completes the other instructions based at least in part on the event register becoming set wherein the other instructions confirm that the event register is set by the first processing action rather than a false positive event; and
executing, by the ARM processor component, a second processing action based at least in part on completion of the waiting function.

16. The method of claim 15 , wherein the first processing action and the second processing action are an ordered set of actions of a workload, and the waiting function ensures that the second processing action is performed after the first processing action.

17. The method of claim 15 , wherein the ARM processor component comprises a central processing unit, a core, or a thread.

18. The method of claim 15 , wherein the memory agent comprises one of: the ARM processor component, an x86 processor component, or a device comprising a me

Assignees

• VMware LLC

Inventors

• Duchesne Regis
• Warkentin Andrei
• Laplace Cyprien
• Li Ye
• Fainkichen Alexander
• Hiriyuru Shruthi
• Kotian Sunil

Classifications

• G06F9/52

  Program synchronisation; Mutual exclusion, e.g. by means of semaphores · CPC title

• G06F9/30087

  Synchronisation or serialisation instructions · CPC title

• G06F9/30123 Primary

  according to context, e.g. thread buffers · CPC title

• G06F9/30043

  LOAD or STORE instructions; Clear instruction · CPC title

• G06F9/30079

  Pipeline control instructions, e.g. multicycle NOP · CPC title