Execution synchronization and tracking

Patent metadata

Field	Value
Publication number	US-11416749-B2
Application number	US-201816216873-A
Country	US
Kind code	B2
Filing date	Dec 11, 2018
Priority date	Dec 11, 2018
Publication date	Aug 16, 2022
Grant date	Aug 16, 2022

Abstract

An integrated circuit includes a processing engine configured to execute instructions that are synchronized using a set of events. The integrated circuit also includes a set of event registers and an age bit register. Each event in the set of events corresponds to a respective event register in the set of event registers. The age bit register includes a set of age bits, where each age bit in the age bit register corresponds to a respective event register in the set of event registers. Each age bit in the age bit register is configured to be set by an external circuit and to be cleared in response to a value change in a corresponding event register in the set of event registers. Executing the instructions by the processing engine changes a value of an event register in the set of event registers.

First claim

What is claimed is:

1. A method comprising:
generating, by a compiler and based on a model of a neural network, executable instructions to be executed by processing engines in an integrated circuit to implement the neural network;
setting, by a host computer, age bits in a first age bit register associated with a first processing engine, each age bit in the first age bit register corresponding to a respective event in a first set of events;
executing, by the processing engines, the executable instructions, wherein:
executing the executable instructions by the processing engines is synchronized using the first set of events; and
executing the executable instructions by the processing engines causes the processing engines to set or clear event registers for the first set of events, each event register for the first set of events being associated with the first processing engine and corresponding to a respective event in the first set of events and a respective age bit in the first age bit register;

based on a change of value in an event register for the first set of events during executing the executable instructions by the processing engines, clearing the corresponding age bit in the first age bit register;
determining, by the host computer and based on values of the age bits in the first age bit register, that an error has occurred during executing the executable instructions by the processing engines; and
identifying a cause of the error based on values in the event registers for the first set of events.

2. The method of claim 1 , wherein:
the first processing engine is configured to clear an event register associated with the first processing engine before triggering a second processing engine to perform an operation; and
the second processing engine is configured to set the event register associated with the first processing engine after performing the operation.

3. The method of claim 1 , further comprising:
generating, by the first processing engine, a notification message when an event register associated with the first processing engine is set or cleared.

4. The method of claim 1 , further comprising setting, by the host computer, age bits in a second age bit register associated with a second processing engine, wherein:
each age bit in the second age bit register is associated with a respective event in a second set of events;
executing the executable instructions by the processing engines is further synchronized using the second set of events;
executing the executable instructions by the processing engines causes the processing engines to set or clear event registers for the second set of events, each event register for the second set of events associated with the second processing engine and corresponding to a respective event in the second set of events and a respective age bit in the second age bit register;
a corresponding age bit in the second age bit register is cleared when an event register for the second set of events changes values during executing the executable instructions by the processing engines; and
determining that the error has occurred during executing the executable instructions by the processing engines is further based on values of the age bits in the second age bit register.

5. An integrated circuit comprising:
a first processing engine configured to execute instructions synchronized using a first set of events;
a first set of event registers associated with the first processing engine, each event in the first set of events corresponding to a respective event register in the first set of event registers;
a first age bit register associated with the first processing engine, the first age bit register including a first set of age bits, each age bit corresponding to a respective event register in the first set of event registers; and
an interface for accessing the first age bit register,
wherein each age bit in the first age bit register is configured to be set by an external circuit through the interface;
wherein each age bit in the first age bit register is configurable to be cleared in response to a value change in a corresponding event register in the first set of event registers; and
wherein executing the instructions by the first processing engine changes a value of an event register in the first set of event registers.

6. The integrated circuit of claim 5 , wherein the first set of event registers is mapped to a set of memory locations accessible by an external processing engine.

7. The integrated circuit of claim 5 , wherein each age bit in the first age bit register is configurable to be cleared only when the corresponding event register in the first set of event registers is set or only when the corresponding event register in the first set of event registers is cleared.

8. The integrated circuit of claim 5 , wherein the first processing engine is configured to:
clear an event register in the first set of event registers when executing of an instruction; and
wait for the event register to be set.

9. The integrated circuit of claim 8 , further comprising a second processing engine, wherein executing the instruction by the first processing engine triggers the second processing engine to:
perform an operation; and
set the event register after performing the operation.

10. The integrated circuit of claim 9 , wherein:
the second processing engine is configured to execute instructions that are synchronized using a second set of events; and
the integrated circuit further comprises:
a second set of event registers associated with the second processing engine, each event in the second set of events corresponding to a respective event register in the second set of event registers; and
a second age bit register associated with the second processing engine, the second age bit register including a second set of age bits, each age bit in the second set of age bits corresponding to a respective event register in the second set of event registers,
wherein each age bit in the second age bit register is configured to be set by the external circuit; and
wherein each age bit in the second age bit register is configurable to be cleared in response to a value change in a corresponding event register in the second set of event registers.

11. The integrated circuit of claim 5 , wherein the external circuit includes a host processor.

12. The integrated circuit of claim 5 , wherein the first age bit register is accessible through the interface and a control and status register (CSR).

13. The integrated circuit of claim 5 , further comprising an event notification circuit, wherein the event notification circuit is configured to:
detect the value change in the corresponding event register in the first set of event registers;
generate a notification message including an identification of an event corresponding to the event register and a timestamp indicating a time when the value change occurs; and
save the notification message to a memory device.

14. The integrated circuit of claim 5 , wherein the first processing engine is configured to execute the instructions to implement a neural network.

15. A method comprising:
setting, by a processing circuit and based on an instruction from an external circuit, a first age bit from a set of age bits in an age bit register associated with the processing circuit, each age bit in the set of age bits corresponding to a respective event register in a set of event registers associated with the processing circuit, and a value in each event register in the set of event registers indicating a state of a respective event in

Assignees

• Amazon Tech Inc

Inventors

• Bshara Nafea
• Volpe Thomas A

Classifications

• G06N3/063

  using electronic means · CPC title

• G06N3/10 Primary

  Interfaces, programming languages or software development kits, e.g. for simulating neural networks · CPC title

• G06F9/542

  Event management; Broadcasting; Multicasting; Notifications · CPC title

• G06F9/30101

  Special purpose registers · CPC title

• G06F9/3855

  Physics · mapped topic