Fill-in confined cell PCM devices

Patent metadata

Field	Value
Publication number	US-12004434-B2
Application number	US-202017086658-A
Country	US
Kind code	B2
Filing date	Nov 2, 2020
Priority date	Nov 2, 2020
Publication date	Jun 4, 2024
Grant date	Jun 4, 2024

Abstract

A method for manufacturing a phase-change memory device includes providing a substrate including a plurality of bottom electrodes, patterning the substrate to form a plurality of pores in the substrate extending from a surface of the substrate to the bottom electrodes, depositing a phase-change material over the substrate, implanting one or more of a Ge, Sb and Te in the phase-change material to amorphize at least a portion of the phase-change material inside the pore, planarizing the device to exposed the surface of the substrate, and forming a plurality of top electrodes over the pores, in contact with the phase-change material.

First claim

What is claimed is:

1. A method for manufacturing a phase-change memory device comprising:
providing a substrate including a plurality of bottom electrodes;
patterning the substrate to form a plurality of pores in the substrate extending from a surface of the substrate to the bottom electrodes;
depositing a crystalline phase-change material over the substrate, wherein the phase-change material is a GST film, to fill the plurality of pores and create an overburden portion on the surface of the substrate;
implanting one or more of a Ge, Sb and Te in the phase-change material to amorphize the overburden at least a portion of the phase-change material inside the pores, during the implantation, without changing a composition of the GST, and avoiding introduction of impurities other than atoms already in the GST, while controlling an ion flux applied during the implantation such that a self-annealing caused by the implantation does not reach a crystallization temperature of the phase-change material;
planarizing the device to expose the surface of the substrate; and
forming a plurality of top electrodes over the pores, in contact with the phase-change material.

2. The method of claim 1 , wherein the substrate is an interlayer dielectric (ILD), the method further comprising depositing a liner on the surface of the substrate before depositing the phase-change material.

3. The method of claim 1 , wherein the phase-change material is one of crystalline and nano-crystalline.

4. The method of claim 1 , wherein an implantation dose of the at least one of Ge, Sb and Te is less than about 5×10 15 cm −2 .

5. The method of claim 1 , further comprising annealing the phase-change material prior to the implantation.

6. The method of claim 1 , wherein forming the top electrodes further comprises:
depositing a top electrode metal over the pores, in contact with the phase-change material; and
patterning the top electrode metal to form the plurality of top electrodes.

7. The method of claim 1 , further comprising manufacturing at least one wire level on the substrate.

8. A method for manufacturing a phase-change memory device comprising:
providing a substrate including a plurality of bottom electrodes;
patterning the substrate to form a plurality of pores in the substrate extending from a surface of the substrate to the bottom electrodes;
depositing over the substrate a GST film, to fill the plurality of pores and create an overburden portion on the surface of the substrate;
carrying out a planarization process to partially remove the overburden portion;
amorphizing a remaining portion of the overburden and forming an amorphous plug of phase-change material in at least an upper portion of the pore by implanting one or more of Ge Sb and Te in the GST film, the amorphizing of the remaining portion of the overburden and the forming of the amorphous plug occurring during the implantation without changing a composition of the GST, and avoiding introduction of impurities other than atoms already in the GST;
planarizing the device to expose the surface of the substrate; and
forming a plurality of top electrodes over the pores, in contact with the phase-change material.

9. The method of claim 8 , wherein the substrate is an interlayer dielectric (ILD), the method further comprising depositing a liner on the surface of the substrate before depositing the phase-change material.

10. The method of claim 8 , wherein the phase-change material is one of crystalline and nano-crystalline.

11. The method of claim 8 , wherein an implantation dose of the at least one of Ge Sb and Te is less than about 5×10 15 cm −2 .

12. The method of claim 8 , further comprising controlling an ion flux applied during the implantation such that a self-annealing caused by the implantation does not reach a crystallization temperature of the phase change material.

13. The method of claim 8 , further comprising annealing the phase-change material prior to the implantation.

14. The method of claim 8 , further comprising one of doping and intermixing the phase-change material with less than about 20% of N, C, O, Si or Se, or alloys thereof.

15. The method of claim 8 , wherein forming the top electrodes further comprises:
depositing a top electrode metal over the pores, in contact with the phase-change material; and
patterning the top electrode metal to form the plurality of top electrodes.

16. The method of claim 8 , further comprising manufacturing at least one wire level on the substrate.

Assignees

• IBM

Inventors

• Adusumilli Praneet
• Brightsky Matthew Joseph
• Cohen Guy M
• Bruce Robert L

Classifications

• H10N70/8418 Primary

  adapted for focusing electric field or current, e.g. tip-shaped · CPC title

• H10N70/043 Primary

  by implantation · CPC title

• H10N70/066

  by filling of openings, e.g. damascene method · CPC title

• H10N70/231 Primary

  based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect · CPC title

• H10N70/826

  adapted for essentially vertical current flow, e.g. sandwich or pillar type devices · CPC title