Three-dimensional memory array with dual-level peripheral circuits and methods for forming the same

Patent metadata

Field	Value
Publication number	US-12004348-B2
Application number	US-202117347810-A
Country	US
Kind code	B2
Filing date	Jun 15, 2021
Priority date	Jun 15, 2021
Publication date	Jun 4, 2024
Grant date	Jun 4, 2024

Abstract

A bonded assembly includes a memory die that is bonded to a logic die. The memory die includes a three-dimensional memory array located on a memory-side substrate, memory-side dielectric material layers located on the three-dimensional memory array and embedding memory-side metal interconnect structures and memory-side bonding pads, a backside peripheral circuit located on a backside surface of the memory-side substrate, and backside dielectric material layers located on a backside of the memory-side substrate and embedding backside metal interconnect structures. The logic die includes a logic-side peripheral circuit located on a logic-side substrate, and logic-side dielectric material layers located between the logic-side substrate and the memory die and embedding logic-side metal interconnect structures and logic-side bonding pads that are bonded to a respective one of the memory-side bonding pads.

First claim

What is claimed is:

1. A bonded assembly comprising a memory die that is bonded to a logic die, wherein:
the memory die comprises:
a three-dimensional memory array located on a memory-side substrate;
memory-side dielectric material layers located on a first side of a combination of the three-dimensional memory array and the memory-side substrate;
memory-side metal interconnect structures and memory-side bonding pads embedded in the memory-side dielectric material layers;
a backside peripheral circuit comprising a first subset of logic devices configured to control operation of the three-dimensional memory array and located on a backside surface of the memory-side substrate;
backside dielectric material layers located on a second side of the combination of the three-dimensional memory array and the memory-side substrate that is an opposite side of the first side; and
backside metal interconnect structures that provide electrical connection between the three-dimensional memory array and the backside peripheral circuit embedded in the backside dielectric material layers; and

the logic die comprises:
a logic-side peripheral circuit comprising a second subset of the logic devices configured to control operation of the three-dimensional memory array and located on a logic-side substrate;
logic-side dielectric material layers located between the logic-side substrate and the memory die;
logic-side metal interconnect structures embedded in the logic-side dielectric material layers; and
logic-side bonding pads that are bonded to a respective one of the memory-side bonding pads and are embedded in the logic-side dielectric material layers,
wherein:
the three-dimensional memory array comprises an alternating stack of insulating layers and electrically conductive layers, memory openings vertically extending through the alternating stack, and memory opening fill structures located within the memory openings and comprising a respective vertical stack of memory elements; and
the alternating stack further comprises a staircase region in which all of the electrically conductive layers have variable lateral extents that decrease with a vertical distance from a horizontal plane including bonding surfaces of the memory-side bonding pads, wherein:
the first subset of logic devices comprises word line drivers configured to apply control voltages to the electrically conductive layers;
all of the word line drivers of the bonded assembly are located on the backside surface of the memory-side substrate and
the electrically conductive layers comprise word lines of the three-dimensional memory array.

2. The bonded assembly of claim 1 , further comprising backside trenches laterally extending along a horizontal direction and vertically extending through the alternating stack and extending to the memory-side substrate.

3. The bonded assembly of claim 1 , wherein:
the alternating stack further comprises a stepped dielectric material portion in contact with stepped surfaces of the alternating stack in the staircase region, having a variable lateral extent that increases stepwise with a vertical distance from an interface between the memory die and the logic die, and having a planar horizontal surface located within a horizontal plane including the backside surface of the memory-side substrate and contacting a sidewall of the memory-side substrate; and
each of the memory opening fill structures further comprises a vertical semiconductor channel.

4. The bonded assembly of claim 3 , further comprising layer contact via structures that contact horizontal surfaces of a respective one of the electrically conductive layers within the staircase region, vertically extend from the respective one of the electrically conductive layers along a vertical direction away from a bonding interface between the memory die and the logic die, and are electrically connected to a respective one of the backside metal interconnect structures.

5. The bonded assembly of claim 2 , further comprising backside trench fill structures located within the backside trenches and comprising dielectric surfaces that contact sidewalls of the alternating stack and the memory-side substrate.

6. The bonded assembly of claim 4 , wherein:
the memory-side metal interconnect structures comprise bit lines of the three-dimensional memory array;
the second subset of logic devices in the logic die comprises bit line drivers configured to drive the bit lines; and
the memory-side metal interconnect structures, the logic-side metal interconnect structures, the memory-side bonding pads, and the logic-side bonding pads comprise electrically conductive paths that provide electrical connection between the bit lines and the bit line drivers.

7. The bonded assembly of claim 3 , wherein:
the memory-side substrate comprises a single crystalline semiconductor material;
the first subset of logic devices within the backside peripheral circuit comprises first field effect transistors including source regions and drain regions that are doped portions of the single crystalline semiconductor material; and
gate electrodes of the first field effect transistors are more distal from the logic die than the source regions and the drain regions of the first field effect transistors are from the logic die.

8. The bonded assembly of claim 7 , wherein the memory-side substrate comprises:
an insulating layer in contact with the single crystalline semiconductor material; and
a doped semiconductor material layer in contact with the memory opening fill structures.

9. The bonded assembly of claim 8 , wherein:
each of the memory opening fill structures further comprises a respective vertical semiconductor channel located in proximity to the respective vertical stack of memory elements and having a doping of a first conductivity type; and
the doped semiconductor material layer is in contact with each of the vertical semiconductor channels.

10. The bonded assembly of claim 8 , wherein the doped semiconductor material layer comprises a single crystalline semiconductor material layer.

11. The bonded assembly of claim 10 , wherein each of the memory opening fill structures comprises a respective pedestal channel portion comprising a single crystalline semiconductor material portion having a single crystalline lattice structure in epitaxial alignment with a single crystalline semiconductor material of the doped semiconductor material layer.

12. The bonded assembly of claim 3 , wherein:
the memory-side substrate comprises a substrate semiconductor layer; and
active regions of the first subset of logic devices are located within the substrate semiconductor layer.

13. The bonded assembly of claim 12 , wherein:
a sidewall of the substrate semiconductor layer contacts the stepped dielectric material portion;
a sidewall of the insulating layer contacts the stepped dielectric material portion; and
the sidewall of the substrate semiconductor layer is vertically coincident with the sidewall of the insulating layer.

14. The bonded assembly of claim 13 , wherein:
a sidewall of the doped semiconductor material layer contacts the stepped dielectric material portion; and
the sidewall of the doped semiconductor material layer is vertically coincident with the sidewall of the insulating layer.

15. The bonded assembly of claim 12 , wherein:
the substrate semiconductor layer comprises a single crystalline semiconductor material; and
the doped semiconductor material layer comprises a polycrystalline semiconductor material.

16. The bonded assembly of claim 12 , furthe

Assignees

• Sandisk Technologies Llc

Inventors

• Mizutani Yuki
• Toyama Fumiaki
• Higashitani Masaaki

Classifications

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H10W99/00

  Subject matter not provided for in other groups of this subclass · CPC title

• H10W90/792

  between multiple chips · CPC title

• H10B43/27 Primary

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title

• H01L23/5283

  Electricity · mapped topic