Printed circuit board

Patent metadata

Field	Value
Publication number	US-12004296-B2
Application number	US-202217712327-A
Country	US
Kind code	B2
Filing date	Apr 4, 2022
Priority date	Dec 22, 2021
Publication date	Jun 4, 2024
Grant date	Jun 4, 2024

Abstract

A printed circuit board includes: an insulating member; a first wiring layer disposed in the insulating member, and including first and second pattern layers spaced apart from each other based on a thickness direction of the printed circuit board; and a second wiring layer disposed in the insulating member, and spaced apart from the first pattern layer over the first pattern layer based on the thickness direction. Based on the thickness direction, an insulation distance between the first pattern layer and the second pattern layer is smaller than an insulation distance between the first pattern layer and the second wiring layer, and each of the first and second pattern layers is thinner than the second wiring layer.

First claim

What is claimed is:

1. A printed circuit board comprising:
an insulating member;
a first wiring layer disposed in the insulating member, and including a first pattern layer and a second pattern layer spaced apart from each other based on a thickness direction of the printed circuit board;
a second wiring layer disposed in the insulating member, and spaced apart from the first pattern layer over the first pattern layer based on the thickness direction; and
a third wiring layer disposed in the insulating member, and spaced apart from the second pattern layer over the second pattern layer based on the thickness direction,
wherein, based on the thickness direction, an insulation distance between the first pattern layer and the second pattern layer is smaller than an insulation distance between the first pattern layer and the second wiring layer and an insulation distance between the second pattern layer and the third wiring layer, and
each of the first and second pattern layers is thinner than the second wiring layer and the third wiring layer.

2. The printed circuit board of claim 1 , wherein each of the first and second pattern layers includes a signal pattern layer, and
each of the second and third wiring layers includes a ground pattern layer.

3. The printed circuit board of claim 1 , wherein a pitch between patterns in each of the first and second pattern layers is larger than a thickness of the patterns in each of the first and second pattern layers.

4. The printed circuit board of claim 3 , wherein P1/2>h1>P1/8, and P2/2>h2>P2/8, where P1 is the pitch between patterns in the first pattern layer, P2 is the pitch between patterns in the second pattern layer, h1 is the thickness of the patterns in the first pattern layer, and h2 is the thickness of the patterns in the second pattern layer.

5. The printed circuit board of claim 1 , wherein a pitch between patterns in each of the first and second pattern layers is larger than the insulation distance between the first and second pattern layers based on the thickness direction.

6. The printed circuit board of claim 5 , wherein P1/2>d1>P1/8, and P2/2>d1>P2/8, where P1 is the pitch between patterns in the first pattern layer, P2 is the pitch between patterns in the second pattern layer, and d1 is the insulation distance between the first and second pattern layers based on the thickness direction.

7. The printed circuit board of claim 1 , wherein, in a plan view, at least a portion of the second pattern layer is disposed in a region between patterns of the first pattern layer not to overlap the first pattern layer.

8. The printed circuit board of claim 7 , wherein, in the plan view, an area of a region of the second pattern layer that does not overlap the first pattern layer is larger than an area of a region of the second pattern layer that overlaps the first pattern layer.

9. The printed circuit board of claim 1 , wherein, in a plan view, at least a portion of the second pattern layer is disposed over the first pattern layer to overlap the first pattern layer.

10. The printed circuit board of claim 9 , wherein, in the plan view, an area of a region of the second pattern layer that overlaps the first pattern layer is larger than an area of a region of the second pattern layer that does not overlap the first pattern layer.

11. The printed circuit board of claim 1 , wherein, in a cross-sectional view, a thickness of a pattern is smaller than a line width of the pattern in each of the first and second pattern layers.

12. A printed circuit board comprising:
an insulating member;
an upper wiring layer and a lower wiring layer disposed in the insulating member; and
a first pattern layer and a second pattern layer spaced apart from each other based on a thickness direction of the printed circuit board, the first pattern layer disposed between the upper wiring layer and the second pattern layer, and the second pattern layer disposed between the lower wiring layer and the first pattern layer,
wherein, based on the thickness direction, an insulation distance between the first pattern layer and the second pattern layer is smaller than an insulation distance between the first pattern layer and the upper wiring layer and an insulation distance between the second pattern layer and the lower wiring layer, and
in a plan view, patterns of the first pattern layer and patterns of the second pattern layer are alternately disposed.

13. The printed circuit board of claim 12 , wherein, in the plan view, an area of a region of the second pattern layer that does not overlap the first pattern layer is larger than an area of a region of the second pattern layer that overlaps the first pattern layer.

14. The printed circuit board of claim 12 , wherein a pitch between the patterns in each of the first and second pattern layers is larger than the insulation distance between the first and second pattern layers based on the thickness direction.

15. The printed circuit board of claim 12 , wherein each of the first and second pattern layers includes a signal pattern layer, and
each of the upper and lower wiring layers includes a ground pattern layer.

Assignees

• Samsung Electro Mech

Inventors

• Lee Jin Uk
• Hwang Chi Won
• Kim Eun Sun
• Ji Yong Wan
• You Young Hun

Classifications

• H05K1/115 Primary

  Via connections; Lands around holes or via connections (H05K1/112 takes precedence) · CPC title

• H05K1/0218

  by printed shielding conductors, ground planes or power plane (H05K1/0236 takes precedence) · CPC title

• H05K1/0265 Primary

  characterized by the lay-out of or details of the printed conductors, e.g. reinforced conductors, redundant conductors, conductors having different cross-sections · CPC title

• H05K1/0298 Primary

  Multilayer circuits · CPC title

• H05K2201/0191

  wherein the thickness of the dielectric plays an important role · CPC title