Method for manufacturing semiconductor structure and semiconductor structure

Patent metadata

Field	Value
Publication number	US-12002864-B2
Application number	US-202117449637-A
Country	US
Kind code	B2
Filing date	Sep 30, 2021
Priority date	Jan 4, 2021
Publication date	Jun 4, 2024
Grant date	Jun 4, 2024

Abstract

A method for manufacturing the semiconductor structure includes: providing a substrate, in which active regions and isolation regions are formed; forming grooves in the active regions, which include first grooves located at upper portions and second grooves located at lower portions and communicating with the first grooves, and a width of the first grooves is greater than a width of the second grooves; and forming gate structures in the first grooves and the second grooves.

First claim

What is claimed is:

1. A method for manufacturing a semiconductor structure, comprising:
providing a substrate, wherein active regions and isolation regions for isolating the active regions are formed in the substrate;
forming grooves in the active regions, wherein the grooves comprise first grooves located at upper portions and second grooves located at lower portions and communicating with the first grooves, and a width of the first grooves is greater than a width of the second grooves;
forming gate structures in the first grooves and the second grooves; and
wherein said forming the grooves in the active regions comprises:
forming a first isolation layer on the substrate, and patterning the first isolation layer to form first openings in the first isolation layer corresponding to the active regions;
patterning the substrate along the first openings to form the first grooves in the active regions;
forming sacrificial layers in the first grooves and the first openings, wherein the first grooves and the first openings are filled up with the sacrificial layers;
forming second openings in the sacrificial layers, wherein a width of the second opening is smaller than a width of the first openings; and
patterning the substrate along the second openings to form the second grooves in the active regions.

2. The method for manufacturing the semiconductor structure of claim 1 , further comprising: after said patterning the substrate along the first openings to form the first grooves in the active regions, and prior to said forming the sacrificial layers in the first grooves and the first openings,
forming first oxide layers on the side walls and bottom walls of the first grooves.

3. The method for manufacturing the semiconductor structure of claim 2 , wherein said forming the second openings in the sacrificial layers comprises:
forming a photoresist layer on the first isolation layer, and patterning the photoresist layer to form third openings on the photoresist layer; and
patterning the sacrificial layers along the third openings to form second openings in the sacrificial layers.

4. The method for manufacturing the semiconductor structure of claim 3 , wherein said forming the photoresist layer on the first isolation layer comprises:
forming a mask layer on the first isolation layer, wherein the photoresist layer is located on the mask layer.

5. The method for manufacturing the semiconductor structure of claim 4 , further comprising: after said patterning the substrate along the second openings to form the second grooves in the active regions,
removing the photoresist layer, the mask layer and the sacrificial layers such that step surfaces are formed between the first grooves and the second grooves.

6. The method for manufacturing the semiconductor structure of claim 5 , further comprising: after said removing the photoresist layer, the mask layer and the sacrificial layers such that step surfaces are formed between the first grooves and the second grooves,
forming second oxide layers on the side walls and bottom walls of the second grooves, wherein the second oxide layers are connected with the first oxide layers; and
forming a barrier layer on the first oxide layers and the second oxide layers, wherein the barrier layer extends to an outside of the first grooves and covers a surface of the first isolation layer.

7. The method for manufacturing the semiconductor structure of claim 6 , wherein said forming the gate structures in the first grooves and the second grooves comprises:
forming a conductive layer in the first grooves and the second grooves, wherein the first grooves and the second grooves are filled up with the conductive layer, and the conductive layer extends to the outside of the first grooves and covers a surface of the barrier layer;
removing the conductive layer and the barrier layer outside the first grooves; and
removing a portion of the conductive layer and a portion of the barrier layer in the first grooves to form the gate structures.

8. The method for manufacturing the semiconductor structure of claim 7 , wherein a top surface of the barrier layer is lower than a top surface of the conductive layer; and
the top surface of the conductive layer is lower than a top surface of a first oxide layer.

9. The method for manufacturing the semiconductor structure of claim 8 , further comprising: after said removing a portion of the conductive layer and a portion of the barrier layer in the first grooves to form the gate structures,
forming a second isolation layer in the first grooves, wherein a top surface of the second isolation layer is flush with a top surface of the first isolation layer.

10. The method for manufacturing the semiconductor structure of claim 1 , wherein said forming the first isolation layer on the substrate comprises:
forming a substrate oxide layer on the substrate, wherein the substrate oxide layer is located below the first isolation layer.

11. A semiconductor structure, comprising:
a substrate, wherein active regions and isolation regions for isolating the active regions are arranged in the substrate;
grooves arranged in the active regions, wherein the grooves comprise first grooves located at upper portions and second grooves located at lower portions and communicating with the first grooves, and a width of the first grooves is greater than a width of the second grooves, such that step surfaces are formed between the first grooves and the second grooves; and
gate structures arranged in the first grooves and the second grooves; wherein top surfaces of the gate structures are lower than top surfaces of the first grooves.

12. The semiconductor structure of claim 11 , wherein a depth of the first grooves is 20 nm to 100 nm, the width of the first grooves is 10 nm to 90 nm, a depth of the second grooves is 50 nm to 300 nm, and the width of the second grooves is 5 nm to 60 nm.

13. The semiconductor structure of claim 12 , wherein a gate structure comprises:
an oxide layer, wherein the oxide layer covers the side walls and bottom wall of the second groove, as well as the step surfaces and the side walls of the first groove;
a barrier layer, wherein the barrier layer covers the surface of the oxide layer, and a top surface of the barrier layer is lower than a top surface of the oxide layer; and
a conductive layer, wherein the conductive layer covers a surface of the barrier layer and fills the second groove and a portion of the first groove, and a top surface of the conductive layer is higher than a top surface of the barrier layer and lower than a top surface of the oxide layer.

14. The semiconductor structure of claim 13 , wherein a height difference between the top surface of the barrier layer and the top surface of the conductive layer is 0 nm to 25 nm.

15. The semiconductor structure of claim 14 , wherein a material of the barrier layer comprises titanium nitride.

16. The semiconductor structure of claim 11 , further comprising a substrate oxide layer, and the substrate oxide layer is arranged on the substrate.

17. The semiconductor structure of claim 16 , further comprising an isolation layer, wherein the isolation layer is arranged in the first grooves, fills up the first grooves, and extends to an outside of the first grooves.

18. The semiconductor structure of claim 17 , wherein the isolation layer comprises first isolation layer and second isolation layer connected with the first isolation layer, the first isolation layer is arranged on a top surface of the substrate oxide layer distal to t

Assignees

• Changxin Memory Tech Inc

Inventors

• Wan Wei
• Wang Pan
• Wang Xuesheng

Classifications

• H10D64/519

  characterised by their top-view geometrical layouts · CPC title

• H10D64/518

  characterised by their lengths or sectional shapes · CPC title

• H10D64/514

  characterised by the insulating layers · CPC title

• H10D64/01

  Manufacture or treatment · CPC title

• H10D64/513 Primary

  within recesses in the substrate, e.g. trench gates, groove gates or buried gates · CPC title