ESD diode solution for nanoribbon architectures

Patent metadata

Field	Value
Publication number	US-11996403-B2
Application number	US-201916713656-A
Country	US
Kind code	B2
Filing date	Dec 13, 2019
Priority date	Dec 13, 2019
Publication date	May 28, 2024
Grant date	May 28, 2024

Abstract

Embodiments disclosed herein include semiconductor devices and methods of forming such devices. In an embodiment, a semiconductor device comprises a semiconductor substrate and a source. The source has a first conductivity type and a first insulator separates the source from the semiconductor substrate. The semiconductor device further comprises a drain. The drain has a second conductivity type that is opposite from the first conductivity type, and a second insulator separates the drain from the semiconductor substrate. In an embodiment, the semiconductor further comprises a semiconductor body between the source and the drain, where the semiconductor body is spaced away from the semiconductor substrate.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a semiconductor substrate;
a source, the source having a first conductivity type, wherein a first insulator separates the source from the semiconductor substrate;
a drain, the drain having a second conductivity type that is opposite from the first conductivity type, wherein a second insulator separates the drain from the semiconductor substrate; and
a semiconductor body between the source and the drain, wherein the semiconductor body is spaced away from the semiconductor substrate, wherein the semiconductor body comprises a first region adjacent to the source and a second region adjacent to the drain, the first region in physical contact with the second region and wherein the first region has the first conductivity type and the second region has the second conductivity type, and wherein a portion of the first region that has the first conductivity type is in direct physical contact with a portion of the second region that has the second conductivity type.

2. The semiconductor device of claim 1 , wherein a first dopant concentration of the first region is less than a second dopant concentration of the source, and wherein a third dopant concentration of the second region is less than a fourth dopant concentration of the drain.

3. The semiconductor device of claim 1 , wherein a first length of the first region is equal to a second length of the second region.

4. The semiconductor device of claim 1 , further comprising:
a pair of spacers comprising a first spacer adjacent to the source and a second spacer adjacent to the drain, wherein the semiconductor body passes through the pair of spacers.

5. The semiconductor device of claim 4 , wherein the first insulator and the second insulator are the same material as the pair of spacers.

6. The semiconductor device of claim 4 , further comprising:
a dummy gate structure between the pair of spacers, wherein the dummy gate structure comprises:
a gate dielectric around the semiconductor body; and
a gate electrode around the gate dielectric.

7. The semiconductor device of claim 6 , wherein the gate electrode is not electrically connected to circuitry outside of the semiconductor device.

8. The semiconductor device of claim 1 , wherein the semiconductor body is a nanowire or a nanoribbon.

9. An electrostatic discharge (ESD) diode, comprising:
a source, wherein the source is a first conductivity type;
a drain, wherein the drain is a second conductivity type that is different than the first conductivity type; and
a plurality of semiconductor bodies between the source and the drain, wherein a depletion region of the ESD diode is along a length of the plurality of semiconductor bodies, wherein the semiconductor bodies comprise a first region adjacent to the source and a second region adjacent to the drain, the first region in physical contact with the second region, and wherein the first region has the first conductivity type and the second region has the second conductivity type, and wherein a portion of the first region that has the first conductivity type is in direct physical contact with a portion of the second region that has the second conductivity type.

10. The ESD diode of claim 9 , wherein the depletion region is substantially equidistant between the source and the drain.

11. The ESD diode of claim 9 , further comprising:
a dummy gate structure, comprising:
a pair of spacers, wherein a first spacer is adjacent to the source and a second spacer is adjacent to the drain;
a gate dielectric surrounding the plurality of semiconductor bodies; and
a gate electrode surrounding the gate dielectric.

Assignees

• Intel Corp

Inventors

• Nidhi Nidhi
• Ramaswamy Rahul
• Hafez Walid M
• Chang Hsu-Yu
• Chang Ting
• Fallahazad Babak
• Trivedi Tanuj
• Kim Jeong Dong
• Kar Ayan
• Orr Benjamin

Classifications

• H10D8/825

  Diodes having bulk potential barriers, e.g. Camel diodes, planar doped barrier diodes or graded bandgap diodes · CPC title

• H10D62/121 Primary

  oriented parallel to substrates · CPC title

• H10D89/611 Primary

  using diodes as protective elements · CPC title

• H10D8/045

  of PN junction diodes · CPC title

• H10D30/6757

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title