Non-volatile memory cell with multiple ferroelectric memory elements (FMEs)

Patent metadata

Field	Value
Publication number	US-11996144-B2
Application number	US-202217840779-A
Country	US
Kind code	B2
Filing date	Jun 15, 2022
Priority date	Jun 15, 2021
Publication date	May 28, 2024
Grant date	May 28, 2024

Abstract

A non-volatile memory (NVM) is formed of memory cells each having multiple ferroelectric memory elements (FMEs). Each FME stores data in relation to an electrical polarity of a recording layer formed of ferroelectric or anti-ferroelectric material. Each multi-FME memory cell is coupled to a set of external control lines activated by a control circuit in a selected order to perform program and/or read operations upon the FMEs. The FMEs may share a nominally identical construction or may have different constructions. Data are programmed and written responsive to the respective program/read responses of the FMEs. Constructions can include ferroelectric tunneling junctions (FTJs), ferroelectric random access memory (FeRAM), and ferroelectric field effect transistors (FeFETs). The NVM may form a portion of a data storage device, such as a solid-state drive (SSD).

First claim

What is claimed is:

1. An apparatus comprising:
a non-volatile memory (NVM) comprising an array of semiconductor memory cells, each memory cell comprising first and second ferroelectric memory elements (FMEs), each of the first and second FMEs having at least one ferroelectric to store at least one bit in the memory cell; and
a control circuit configured to activate a common set of external control lines, coupled to a selected memory cell, in a selected order to read the at least one bit from the selected memory cell, wherein the selected order comprising applying a first set of control inputs to program the first FME and subsequently applying a second set of control inputs to program the second FME, the second FME requiring power level lower than the power level required by the first FME.

2. The apparatus of claim 1 , wherein the first and second FMEs have a nominally identical construction.

3. The apparatus of claim 1 , wherein each of the first and second FMEs has a different construction.

4. The apparatus of claim 1 , wherein the control circuit is further configured to activate the first FME in the selected memory cell while retaining the remaining second FME in the selected memory cell in an inactive state in order to retrieve the at least one bit from the selected memory cell.

5. The apparatus of claim 1 , wherein the control circuit is further configured to activate the common set of external control lines coupled to the selected memory cell in a second selected order to program the at least one bit to the selected memory cell.

6. The apparatus of claim 1 , wherein the first and second FMEs are arranged in parallel within the selected memory cell.

7. The apparatus of claim 1 , wherein the first and second FMEs are arranged in series within the selected memory cell.

8. The apparatus of claim 1 , wherein at least a selected one of the first or second FMEs is characterized as a ferroelectric tunneling junction (FTJ), a ferroelectric random access memory (FeRAM) memory cell having at least one transistor and at least one capacitor, or a ferroelectric field effect transistor (FeFET).

9. The apparatus of claim 1 , wherein each of the first and second FMEs are nominally identical and the first FME is physically inverted with respect to the second FME within the selected memory cell.

10. The apparatus of claim 1 , wherein the NVM is a stack register which forms a portion of a data storage device having a main memory store to store user data from a client device.

11. The apparatus of claim 1 , wherein the NVM is a main data store of a solid-state drive (SSD).

12. The apparatus of claim 1 , wherein the selected memory cell further comprises a volatile memory element.

13. The apparatus of claim 1 , wherein the NVM is characterized as a selected one of a write cache, a read buffer, or a local processor memory of a solid-state drive (SSD).

14. A data storage device, comprising:
a non-volatile memory cell comprising first and second ferroelectric memory elements (FMEs) interconnected with a common set of external control lines and each having a different program/read response, wherein the second FME requiring power level lower than the power level required by the first FME; and
a controller circuit configured to program data to and read data from the FMEs by directing control signals to the external control lines in respective orders, wherein the respective order comprising applying a first set of control inputs to program the first FME and subsequently applying a second set of control inputs to program the second FME.

15. The data storage device of claim 14 , wherein the controller is configured to program first data to the respective first and second FMEs by applying a first set of control signals to the external control lines in a first order, and wherein the controller is configured to program second data to the respective first and second FMEs by applying a second set of control signals to the external control lines in a different, second order.

16. The data storage device of claim 14 , wherein the controller is configured to read first data from the respective first and second FMEs by applying a first set of control signals to the external control lines in a first order, and wherein the controller is configured to read second data to the respective first and second FMEs by applying a second set of control signals to the external control lines in a different, second order.

17. The data storage device of claim 14 , wherein the first and second FMEs share a common, nominally identical construction.

18. The data storage device of claim 14 , wherein the first and second FMEs have different respective constructions.

19. The data storage device of claim 14 , where each of the first and second FMEs have a selected one of a ferroelectric tunneling junction (FTJ) construction, a ferroelectric random access memory (FeRAM) construction, or a ferroelectric field effect transistor (FeFET) construction.

20. The data storage device of claim 14 , wherein the first FME has a ferroelectric layer formed of ferroelectric material and the second FME has an anti-ferroelectric layer formed of anti-ferroelectric material.

Assignees

• Seagate Technology Llc

Inventors

• Trantham Jon D
• Viraraghavan Praveen
• Dykes John W
• Gilbert Ian J
• Kalarickal Sangita Shreedharan
• Totin Matthew J
• El-Batal Mohamad
• Mehta Darshana H

Classifications

• G11C11/5657 Primary

  using ferroelectric storage elements · CPC title

• G11C11/221 Primary

  using ferroelectric capacitors · CPC title

• G11C11/223

  using MOS with ferroelectric gate insulating film · CPC title

• G11C11/2273

  Reading or sensing circuits or methods · CPC title

• G11C11/2275

  Writing or programming circuits or methods · CPC title