Resistive memory architectures with multiple memory cells per access device

Patent metadata

Field	Value
Publication number	US-10797237-B2
Application number	US-201916542174-A
Country	US
Kind code	B2
Filing date	Aug 15, 2019
Priority date	May 31, 2007
Publication date	Oct 6, 2020
Grant date	Oct 6, 2020

Abstract

A resistive memory structure, for example, phase change memory structure, includes one access device and two or more resistive memory cells. Each memory cell is coupled to a rectifying device to prevent parallel leak current from flowing through non-selected memory cells. In an array of resistive memory bit structures, resistive memory cells from different memory bit structures are stacked and share rectifying devices.

First claim

What is claimed is:

1. A memory device, comprising:
a first stacked memory structure including a first memory cell and a second memory cell;
an electrode operatively coupling the first memory cell and the second memory cell to a cell select line;
a first access device operatively coupled with the first memory cell; and
a second stacked memory structure including a third memory cell and a fourth memory cell, wherein the electrode operatively couples the third memory cell and the fourth memory cell to the cell select line.

2. The memory device of claim 1 , further comprising:
a first rectifying device operatively coupled to the first memory cell and the first access device.

3. The memory device of claim 1 , further comprising:
a second access device operatively coupled to the second memory cell.

4. The memory device of claim 3 , further comprising:
a third rectifying device operatively coupled to the second memory cell and the second access device.

5. The memory device of claim 3 , wherein:
a position of the second access device is offset in a horizontal direction from the position of the first stacked memory structure.

6. The memory device of claim 1 , further comprising:
a second rectifying device operatively coupled to the electrode and the cell select line.

7. The memory device of claim 1 , wherein the first memory cell and the second memory cell each comprise a phase change memory cell.

8. The memory device of claim 1 , wherein the first memory cell and the second memory cell each comprise a resistive memory cell.

9. The memory device of claim 1 , wherein a top surface of the first memory cell is in contact with a first surface of the electrode and a top surface of the second memory cell is in contact with a second surface of the electrode different from the first surface.

10. The memory device of claim 1 , wherein the third memory cell and the fourth memory cell each comprise a resistive memory cell or a phase change memory cell.

11. The memory device of claim 1 , wherein the first access device is operatively coupled to the third memory cell.

12. The memory device of claim 1 , wherein the first memory cell, the second memory cell, the third memory cell and the fourth memory cell each share at least a portion of the electrode.

13. The memory device of claim 1 , wherein the first memory cell, the second memory cell, the third memory cell and the fourth memory cell are each coupled with separate word lines.

14. A device, comprising:
an array of pairs of stacked memory cells;
an electrode operatively coupling a first pair of memory cells and a second pair of memory cells, the electrode coupled with a cell select line; and
an access device operatively coupled with the first pair of memory cells and the second pair of memory cells, the access device configured to control current flow through the first pair of memory cells and the second pair of memory cells.

15. The device of claim 14 , further comprising:
a plurality of rectifying devices, each rectifying device being connected to a memory cell.

16. The device of claim 15 , further comprising:
a first rectifying device configured between the first pair of memory cells and the access device; and
a second rectifying device configured between the second pair of memory cells and the access device.

17. The device of claim 15 , wherein the plurality of rectifying devices are combined into a single rectifying device.

18. The device of claim 17 , wherein the single rectifying device is coupled with the electrode.

19. The device of claim 14 , wherein the first pair of memory cells and the second pair of memory cells share a single rectifying device.

20. A memory device, comprising:
an array of pairs of stacked memory cells;
an electrode shared by at least one memory cell of a first pair of memory cells and at least one other memory cell of a second pair of memory cells, the electrode coupled with a cell select line; and
an access device operatively coupled with the first pair of memory cells and the second pair of memory cells, the access device configured to control a flow of current through the first pair of memory cells and the second pair of memory cells during an access operation.

Assignees

• Ovonyx Memory Tech Llc
• Micron Technology Inc

Inventors

• Liu Jun
• Violette Michael P

Classifications

• G11C13/0004 Primary

  comprising amorphous/crystalline phase transition cells · CPC title

• G11C16/00

  Erasable programmable read-only memories (G11C14/00 takes precedence) · CPC title

• G11C16/02 Primary

  electrically programmable · CPC title

• G11C2213/78

  Array wherein the memory cells of a group share an access device, all the memory cells of the group having a common electrode and the access device being not part of a word line or a bit line driver · CPC title

• G11C2213/74

  Array wherein each memory cell has more than one access device · CPC title