High speed interface for multi image sensor device

Patent metadata

Field	Value
Publication number	US-11995012-B2
Application number	US-202217695204-A
Country	US
Kind code	B2
Filing date	Mar 15, 2022
Priority date	Mar 15, 2022
Publication date	May 28, 2024
Grant date	May 28, 2024

Abstract

A multi-image sensor system includes data, clock, and control buses, an application processor connected to the data bus and the clock bus, and image sensors connected in a daisy chain using the control bus. A first one of the image sensors configured as a master outputs image data to the data bus, outputs a first clock signal to the clock bus, and sends a control signal to a second one of the image sensors in the daisy chain through the control bus. The control signal has a first logic state when output of the first image data starts and a second other logic state when output of the first image data ends. The second image sensor connects itself to the data bus and the master disconnects itself from the data bus according to a state of the first control signal.

First claim

What is claimed is:

1. A multi-image sensor system comprising:
a data bus;
a clock bus;
a control bus;
an application processor connected to the data bus and the clock bus;
a plurality of image sensors connected together in a daisy chain using the control bus, the image sensors configured to selectively connect to the data bus and the clock bus and a first image sensor among the image sensors is configured as a master,
wherein the master outputs first image data to the data bus, outputs a first clock signal to the clock bus, and sends a first control signal to a second image sensor among the image sensors in the daisy chain through the control bus,
wherein the first control signal has a first logic state when output of the first image data starts and a second other logic state when output of the first image data ends, wherein the second image sensor connects itself to the data bus and the clock bus upon determining that the first control signal has the second logic state, and wherein the master disconnects itself from the data bus and the clock bus a period of time after setting the first control signal to the second logic state.

2. The multi-image sensor system of claim 1 , wherein the second image sensor outputs second image data to the data bus, outputs a second clock signal to the clock bus, and sends a second control signal to a third one of the image sensors in the daisy chain through the control bus after connecting itself to the data bus and the clock bus, wherein the second control signal has the first logic state when output of the second image data starts and the second logic state when output of the second image data ends.

3. The multi-image sensor system of claim 1 , wherein the first control signal includes a synchronization pulse before being set to the first logic state, and the second image sensor is synchronized in response to the synchronization pulse.

4. The multi-image sensor system of claim 2 , wherein the application processor receives the first image data and the second image data from the data bus, receives the first clock signal and the second clock signal from the clock bus, processes the first image data using the first clock signal and the second image data using the second clock signal.

5. The multi-image sensor system of claim 1 , further comprising a hardware interface that enables each of the image sensors to selectively connect to the data bus and the clock bus.

6. The multi-image sensor system of claim 1 , wherein the second image sensor sends an error interrupt to the application processor upon determining that the first control signal has the second logic state but the master is still outputting image data to the data bus.

7. The multi-image sensor system of claim 1 , wherein each image sensor sends a block of its image data less than an entire frame to the application processor and then passes control of the data bus and the clock bus to a next one of the image sensors in the daisy chain.

8. The multi-image sensor system of claim 1 , further comprising glasses, and the image sensors are mounted to the glasses.

9. A multi-image sensor system comprising:
a data bus;
a clock bus;
an application processor connected to the data bus and the clock bus;
a plurality of image sensors configured to selectively connect to the data bus and the clock bus and a first image sensor among the image sensors is configured as a master;
a control bus connected to each of the image sensors for outputting a control signal; and
wherein the master transitions the control signal from a first logic state to a second logic state to perform a synchronization of the other image sensors,
wherein the master outputs first image data to the data bus and outputs a first clock signal to the clock bus while the control signal has the second logic state and sets the control signal to the first logic state after completing output of the first image data,
wherein a second image sensor among the image sensors connects itself to the data bus and the clock bus when a count of pulses of the control signal has a value indicating a turn of the second image sensor,
wherein the master disconnects itself from the data bus and the clock bus a first period of time after setting the control signal to the first logic state.

10. The multi-image sensor system of claim 9 , wherein the second image sensor outputs second image to the data bus and a second clock signal to the clock bus a second period of time after connecting itself to the data bus and the clock bus.

11. The multi-image sensor system of claim 10 , wherein the second period is larger than the first period.

12. The multi-image sensor system of claim 9 , wherein each of the image sensors stores information indicating its order for outputting and the value is determined from the information.

13. The multi-image sensor system of claim 9 , wherein the second image sensor sends an error interrupt to the application processor when a second period of time elapses after connecting itself to the data bus and the clock bus and the master is still outputting image data to the data bus.

14. The multi-image sensor system of claim 9 , further comprising a hardware interface that enables each of the image sensors to selectively connect to the data bus and the clock bus.

15. A multi-image sensor system comprising:
a data bus;
a clock bus;
an application processor connected to the data bus and the clock bus;
a plurality of image sensors configured to selectively connect to the data bus and the clock bus and a first image sensor among the image sensors is configured as a master;
a control bus connected to each of the image sensors; and
a synchronization bus connected to each of the image sensors,
wherein the master outputs a synchronization signal to each of the other image sensors through the synchronization bus to perform a synchronization,
wherein the master outputs first image data to the data bus, outputs a first clock signal to the clock bus, and sends a control signal to each of the other image sensors through the control bus after the synchronization,
wherein the control signal has a first logic state when output of the first image data starts and a second other logic state when output of the first image data ends,
wherein a second image sensor among the image sensors connects itself to the data bus and the clock bus upon determining that the first control signal has the second logic state,
wherein the second image sensor sets the control signal to the first logic state after connecting itself to the data bus and the clock bus, and wherein the master disconnects itself from the data bus and the clock bus after determining that the control signal has been set to the first logic state.

16. The multi-image sensor system of claim 15 , wherein the second image sensor outputs second image data to the data bus and outputs a second clock signal to the clock bus a period of time after setting the control signal to the first logic state.

17. The multi-image sensor system of claim 16 , wherein the second image sensor sets the control signal to the second logic state after completing its output of the second image data.

18. The multi-image sensor system of claim 17 , wherein the second image sensor disconnects itself from the data bus and the clock bus after determining that the control signal has been set to the first logic state after it has set the control signal to the second logic state.

19. The multi-image sensor system of claim 15 , wherein the synchronization signal includes a syn

Assignees

• Samsung Electronics Co Ltd

Inventors

• Klein Avi
• Barash Dror
• Horowitz Guy
• Reinherz Oren
• Herman Roi
• Eisenberg Amit

Classifications

• G06F13/24 Primary

  using interrupt (G06F13/32 takes precedence) · CPC title

• G02B27/017

  Head mounted · CPC title

• G06F13/364

  using independent requests or grants, e.g. using separated request and grant lines · CPC title

• G06F13/4256

  using a clocked protocol · CPC title

• G06F13/4291 Primary

  using a clocked protocol · CPC title