Method and apparatus to enable multiple masters to operate in a single master bus architecture

Patent metadata

Field	Value
Publication number	US-10353837-B2
Application number	US-201615087535-A
Country	US
Kind code	B2
Filing date	Mar 31, 2016
Priority date	Sep 9, 2013
Publication date	Jul 16, 2019
Grant date	Jul 16, 2019

Abstract

To accommodate multiple masters over bus architectures supporting a single master device, a mechanism is provided for an inactive master device to assert an in-band IRQ. A current master then polls the other inactive master devices over a shared data bus to ascertain which inactive master device is asserting the IRQ. Upon identifying the asserting inactive master device, the current master device grants control of the data bus to the new master device, thereby making the inactive master the new active master device.

First claim

What is claimed is:

1. A method operational on a first master device, comprising:
managing communications over a data bus for a plurality of devices coupled to the data bus, wherein two or more master devices are coupled to the data bus;
determining when an in-band interrupt request has been asserted on the data bus;
determining whether the in-band interrupt request on the data bus was asserted by a second master device; and
handing over control of the data bus to the second master device after determining that the second master device asserted the in-band interrupt request.

2. The method of claim 1 , further comprising:
driving a first wire of the data bus to a first signaling state;
releasing control of the first wire, wherein the first wire is initially held in the first signaling state by a pull-up resistor or a pull-down resistor; and
determining that the in-band interrupt request on the data bus was asserted when the first wire is driven to a second signaling state.

3. The method of claim 2 , further comprising:
providing one or more clock pulses on a second wire of the data bus after releasing control of the first wire.

4. The method of claim 2 , further comprising:
providing clock pulses on the first wire prior to releasing control of the first wire.

5. The method of claim 2 , further comprising:
transmitting a heartbeat word on the data bus,
wherein the heartbeat word provides clock information, and
wherein control of the first wire is released during transmission of the heartbeat word.

6. The method of claim 2 , wherein control of the first wire is released when the data bus is idle or when the data bus is an inactive mode of operation.

7. The method of claim 1 , further comprising:
after determining that the in-band interrupt request has been asserted:
transmitting one or more commands to cause one or more devices that asserted the in-band interrupt request to provide their corresponding device identifiers; and
identifying a highest priority device requesting interrupt service based on the device identifiers.

8. The method of claim 1 , wherein handing over control of the data bus to the second master device comprises:
transmitting a command to the second master device.

9. The method of claim 1 , wherein the data bus comprises a two-wire serial bus.

10. A method operational on a first master device coupled to a data bus, comprising:
asserting an in-band interrupt request through the data bus while the data bus is controlled by a second master device;
determining whether the second master device has released control of the data bus after assertion of the in-band interrupt request; and
acquiring control of the data bus when the second master device has released control of the data bus.

11. The method of claim 10 , wherein asserting the in-band interrupt request comprises:
driving a first line of the data bus to a first logic level for a first period of time,
wherein the first period of time occurs between data transmissions on the data bus.

12. The method of claim 10 , further comprising:
determining that a period of time when the second master device is receptive to in-band interrupt requests has commenced;
asserting the in-band interrupt request by driving a first line of the data bus to a first signaling state during the period of time when the second master device is receptive to in-band interrupt requests; and
releasing the first line of the data bus prior to expiration of the period of time when the second master device is receptive to in-band interrupt requests.

13. The method of claim 12 , further comprising:
receiving one or more clock pulses from a second line of the data bus during the period of time when the second master device is receptive to in-band interrupt requests.

14. The method of claim 12 , further comprising:
receiving clock pulses from the first line prior to the period of time when the second master device is receptive to in-band interrupt requests.

15. The method of claim 12 , wherein the period of time when the second master device is receptive to in-band interrupt requests occurs during transmission of a heartbeat word.

16. The method of claim 12 , wherein control of the first line is released when the data bus is idle.

17. The method of claim 12 , further comprising:
transmitting a device identifier to the second master device in response to a command received after asserting the in-band interrupt request.

18. The method of claim 12 , further comprising:
masking signaling transitions on the first line from a clock recovery circuit during the period of time when the second master device is receptive to in-band interrupt requests.

19. The method of claim 10 , further comprising:
transmitting information indicating an intent to voluntarily yield control of the data bus in a command sent to the second master device after acquiring control of the data bus.

20. An apparatus comprising:
a serial data bus having a first wire and a second wire, the first wire being coupled to a pull-up or pull-down resistor; and
a plurality of devices coupled to the serial data bus, including a first master device and a second master device,
wherein the first master device is configured to:
manage communications over the serial data bus for the plurality of devices coupled to the serial data bus;
drive the first wire to a first signaling state;
release control of the first wire, wherein the first wire is initially held in the first signaling state by the pull-up or pull-down resistor; and
determine that an in-band interrupt request on the serial data bus was asserted when the first wire is driven to a second signaling state, and

wherein the second master device is configured to:
determine that a period of time when the first master device is receptive to interrupts has commenced;
assert the in-band interrupt request by driving the first wire of the serial data bus to the second signaling state during the period of time when the first master device is receptive to interrupts; and
release the first wire of the serial data bus prior to expiration of the period of time when the first master device is receptive to interrupts.

21. The apparatus of claim 20 , wherein the first master device is configured to:
provide one or more clock pulses on the second wire of the serial data bus after releasing control of the first wire.

22. The apparatus of claim 20 , wherein the first master device is configured to:
provide clock pulses on the first wire prior to releasing control of the first wire.

23. The apparatus of claim 20 , wherein the second master device is configured to:
mask signaling transitions on the first wire from a clock recovery circuit during the period of time when the first master device is receptive to interrupts.

24. The apparatus of claim 20 , wherein control of the first wire is released during transmission of a heartbeat word.

25. The apparatus of claim 20 , wherein control of the first wire is released when the serial data bus is idle.

26. The apparatus of claim 20 , further comprising:
one or more slave devices coupled to the serial data bus,
wherein the first master device is configured to:
transmit one or more commands addressed to the one or more slave devices and the second master device after determining that the in-band interrupt request has been asserted; and
receive an indication of

Assignees

• Qualcomm Inc

Inventors

• Sengoku Shoichiro
• Wietfeldt Richard Dominic
• Wiley George Alan

Classifications

• G06F11/3027

  where the computing system component is a bus · CPC title

• G06F13/24

  using interrupt (G06F13/32 takes precedence) · CPC title

• G06F13/362

  with centralised access control · CPC title

• G06F13/4256

  using a clocked protocol · CPC title

• G06F13/426

  using an embedded synchronisation, e.g. Firewire bus, Fibre Channel bus, SSA bus · CPC title