Memory module with distributed data buffers

Patent metadata

Field	Value
Publication number	US-11994982-B2
Application number	US-202117202021-A
Country	US
Kind code	B2
Filing date	Mar 15, 2021
Priority date	Jul 16, 2009
Publication date	May 28, 2024
Grant date	May 28, 2024

Abstract

A memory module comprises dynamic random access memory (DRAM) devices arranged in ranks, and a module controller configurable to receive address and control signals for a memory operation, and to output first module control signals to the DRAM devices, causing a selected rank to output or receive N-bit-wide data. The module controller is further configurable to output second module control signals to a plurality of data buffers coupled to the DRAM devices via module data lines. Each respective data buffer includes a n-bit-wide (n<N) data path and logic configurable to, in response to the second module control signals, enable the n-bit-wide data path to receive and regenerate signals carrying a respective n-bit-wide section of the N-bit-wide data communicated from/to a respective n-bit-wide section of the module data lines. The logic is further configurable to disable the n-bit-wide data path when the memory module is not being accessed for data.

First claim

We claim:

1. A memory module operable in a computer system, the computer system including address and control signal lines, data signal lines, one or more module slots for mounting one or more memory modules, and a memory controller configurable to communicate with each of the one or more memory modules via the address and control signal lines and the data signal lines, the memory module comprising:
a module board having an edge connector including a plurality of electrical contacts to be releasably coupled to corresponding contacts of a module slot of the one or more module slots;
memory devices arranged in multiple N-bit-wide ranks on the module board;
a module controller on the module board configurable to receive via the address and control signal lines address and control signals for a memory read or write operation, and to output, first module control signals associated with the memory read or write operation and second module control signals associated with the memory read or write operation, wherein, in response to the first module control signals associated with the memory read or write operation, one of the multiple N-bit-wide ranks is selected to perform the memory read or write operation by outputting or receiving N-bit-wide data associated with the memory read or write operation; and
data buffers distributed along the edge connector of the module board and coupled to the memory devices via module data lines, each respective data buffer being configurable to buffer and transmit a respective n-bit-wide section of the N-bit-wide data between a respective n-bit-wide section of the module data lines and a respective n-bit-wide section of the data signal lines, the respective n-bit-wide section of the data signal lines including a first data signal line, the respective n-bit-wide section of the module data lines including a first module data line corresponding to the first data signal line, the respective data buffer including respective data paths and respective logic configurable to control the respective data paths in response to the second module control signals from the module controller, the respective data paths including a first write data path and a first read data path between the first module data line and the first data signal line, the first write data path including a write input buffer coupled to the first data signal line and a write output driver coupled to the first module data line, the first read data path including a read input buffer coupled to the module data line and a read output driver coupled to the data signal line, wherein, in response to the memory read or write operation being a memory write operation, the respective logic is configured to cause the first write data path to transition from a first configuration to a second configuration and subsequently from the second configuration to the first configuration, wherein the first write data path is disabled in the first configuration and is enabled in the second configuration to receive a first write data bit of a respective n-bit-wide section of N-bit-wide write data from the first data signal line, to pass the first write data bit through the first write data path from the write input buffer to the write output driver, and to drive the first write data bit to the first module data line, wherein, in response to the memory read or write operation being a memory read operation, the respective logic is configured to cause the first read data path to transition from a third configuration to a fourth configuration and subsequently from the fourth configuration to the third configuration, wherein the first read data path is disabled in the third configuration and is enabled in the fourth configuration to receive a first read data bit of a respective n-bit-wide section of N-bit-wide read data from the first module data line, to pass the first read data bit through the first read data path from the read input buffer to the read output driver, and to drive the first read data bit to the first data signal line, wherein N and n are positive integers and n is less than N;
wherein the first read data path is kept at the third configuration during the memory write operation, and the first write data path is kept at the first configuration during the memory read operation; and wherein:
the first write data path is distinct from the first read data path such that, during the memory write operation, the first write data bit is passed from the write input buffer to the write output driver without passing through any portion of the first read data path between the read input buffer and the read output driver, and that, during the memory read operation, the first read data bit is passed from the read input buffer to the read output driver without passing through any portion of the first write data path between the write input buffer and the write output driver; and
the write output driver is tristated when the first write data path is in the first configuration, and the read output driver is tristated when the first read data path is in the third configuration.

2. The memory module of claim 1 , wherein respective n-bit-wide section of the module data lines is coupled to a respective n-bit-wide section of the memory devices, and wherein the respective n-bit-wide section of the memory devices includes one memory device having a bit width of 8 in each of the multiple N-bit-wide ranks or two memory devices each having a bit width of 4 in each of the multiple N-bit-wide ranks.

3. The memory module of claim 1 , wherein each of the module data lines is configurable to carry data from the memory controller to a corresponding memory device in each of the multiple N-bit-wide ranks.

4. The memory module of claim 3 , wherein the first read data bit is received from the first module data line by the read input buffer, and is driven to the first data signal line by the read output driver.

5. The memory module of claim 4 , wherein the read output driver is comparable to an output buffer in one of the memory devices.

6. The memory module of claim 1 , wherein the logic is further configurable, in response to the second module control signals, to keep the first write data path in the second configuration for a time period corresponding to a time period when the first write data bit is passing through the first write data path during the memory write operation, or to keep the read data path in the fourth configuration for a time period corresponding to a time period when the first read data bit is passing through the first read data path during the memory read operation.

7. The memory module of claim 6 , wherein the first write data bit is received from the first data signal line by the write input buffer, and is driven to the first module data line by the write output driver.

8. The memory module of claim 7 , wherein write input buffer is comparable to an input buffer in one of the memory devices so that the respective data buffer is configurable to present a load to the memory controller during the memory write operation that is the same as a load that one of the memory devices would present.

9. The memory module of claim 1 , wherein the address and control signals include input chip select signals corresponding, respectively, to the multiple N-bit-wide ranks and the first module control signals include registered chip select signals corresponding, respectively, to the input chip select signals.

10. The memory module of claim 1 , wherein the read output driver and the write output driver are tristated when the memory controller is accessing another memory module of the one or more memory modules for memory read or write operations.

11. The memory module of claim 1

Assignees

• Netlist Inc

Inventors

• Lee Hyun
• Bhakta Jayesh R

Classifications

• G06F12/00 Primary

  Accessing, addressing or allocating within memory systems or architectures (digital input from, or digital output to record carriers, e.g. to disk storage units, G06F3/06) · CPC title

• G11C5/025 Primary

  Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits, geometrical lay-out of the components in integrated circuits H10D89/10) · CPC title

• G11C5/04

  Supports for storage elements {, e.g. memory modules}; Mounting or fixing of storage elements on such supports · CPC title

• G11C5/066

  Means for reducing external access-lines for a semiconductor memory clip, e.g. by multiplexing at least address and data signals · CPC title

• G11C8/12

  Group selection circuits, e.g. for memory block selection, chip selection, array selection · CPC title