Clock data recovery circuit

Patent metadata

Field	Value
Publication number	US-11994901-B2
Application number	US-202217841255-A
Country	US
Kind code	B2
Filing date	Jun 15, 2022
Priority date	Sep 30, 2019
Publication date	May 28, 2024
Grant date	May 28, 2024

Abstract

A clock data recovery circuit includes a deglitch filter circuit and a timer circuit. The deglitch filter circuit is configured to remove pulses of less than a particular duration from a data signal to produce a deglitched data signal. The timer circuit is coupled to the deglitch filter, and is configured to compare a duration of a pulse of the deglitched data signal to a threshold duration, and identify the pulse as representing a logic one based on the duration of the pulse exceeding the threshold duration.

First claim

What is claimed is:

1. A clock data recovery circuit, comprising:
a deglitch filter circuit configured to output a deglitched data signal including a pulse; and
a timer circuit coupled to the deglitch filter circuit, the timer circuit including:
an oscillator circuit configured to generate a clock signal for a duration of the pulse received from the deglitch filter circuit;
a first latch circuit configured to detect a falling edge of the clock signal; and
a second latch circuit configured to:
responsive to the first latch circuit detecting the falling edge of the clock signal, detect a rising edge of the clock signal; and
responsive to detecting the rising edge of the clock signal, storing a logic one at an end of a threshold duration.

2. The clock data recovery circuit of claim 1 , wherein the timer circuit is configured to identify the pulse as representing a logic zero based on the duration of the pulse not exceeding the threshold duration.

3. The clock data recovery circuit of claim 1 , wherein the second latch circuit includes a flip-flop configured to store the logic one represented by the pulse at the end of the threshold duration.

4. The clock data recovery circuit of claim 3 , further comprising:
a delayed pulse circuit configured to generate, responsive to a leading edge of the pulse, a reset pulse;
wherein the timer circuit is configured to apply the reset pulse to reset the flip-flop.

5. The clock data recovery circuit of claim 4 , wherein the delayed pulse circuit includes:
a delay circuit configured to delay the pulse produce a delayed pulse; and
a pulse generation circuit configured to generate the reset pulse at a leading edge of the delayed pulse.

6. The clock data recovery circuit of claim 1 , wherein:
a full cycle of the clock signal determines the threshold duration.

7. The clock data recovery circuit of claim 6 , wherein the oscillator circuit includes:
a first ramp circuit configured to time a high level of the period; and
a second ramp circuit configured to time a low level of the period.

Assignees

• Texas Instruments Inc

Inventors

• Hanschke Michael Ryan
• Pandey Pankaj
• Pham Joseph
• Evans David Wayne

Classifications

• G06F1/14 Primary

  Time supervision arrangements, e.g. real time clock · CPC title

• G06F11/1604 Primary

  where the fault affects the clock signals of a processing unit and the redundancy is at or within the level of clock signal generation hardware · CPC title

• H04L7/0037

  Delay of clock signal · CPC title

• H04L7/0045

  Correction by a latch cascade · CPC title

• H04L7/0041

  Delay of data signal · CPC title