Clock data recovery circuit

Patent metadata

Field	Value
Publication number	US-11385677-B2
Application number	US-202017039260-A
Country	US
Kind code	B2
Filing date	Sep 30, 2020
Priority date	Sep 30, 2019
Publication date	Jul 12, 2022
Grant date	Jul 12, 2022

Abstract

A clock data recovery circuit includes a deglitch filter circuit and a timer circuit. The deglitch filter circuit is configured to remove pulses of less than a predetermined duration from a data signal to produce a deglitched data signal. The timer circuit is coupled to the deglitch filter, and is configured to compare a duration of a pulse of the deglitched data signal to a threshold duration, and identify the pulse as representing a logic one based on the duration of the pulse exceeding the threshold duration.

First claim

What is claimed is:

1. A clock data recovery circuit, comprising:
a deglitch filter circuit including:
a data input; and
a deglitched data output;

a timer circuit including:
an enable input coupled the deglitched data output;
a bit output; and
a reset input;

a delayed pulse circuit including:
an input coupled to the deglitched data output; and
a pulse output coupled to the reset input; and

a latch including:
a data input coupled to the bit output;
a clock input coupled to the deglitched data output; and
a recovered data output.

2. The clock data recovery circuit of claim 1 , wherein the reset input is a first reset input, and the deglitch filter circuit includes:
a falling edge deglitch filter including
an input coupled to the data input; and
an output;

a rising edge deglitch filter including
an input coupled to the data input; and
an output; and

latch circuitry including:
a second reset input coupled to the output of the falling edge deglitch filter;
a set input coupled to the output of the rising edge deglitch filter; and
an output coupled to the deglitched data output.

3. The clock data recovery circuit of claim 2 , wherein:
the falling edge deglitch filter includes:
a first inverter including:
a first inverter input coupled to the data input; and
a first inverter output;

a second inverter including:
a second inverter input coupled to the first inverter output; and
a second inverter output;

a first resistor including:
a first resistor terminal; and
a second resistor terminal coupled to the second inverter output;

a first capacitor coupled between the first resistor terminal and a ground terminal;
a first switch coupled between the first resistor terminal and the ground terminal, the first switch including a first control input coupled to the first inverter output; and
a first Schmitt trigger circuit including:
an input coupled to the first resistor terminal; and
an output coupled to the second reset input; and

the rising edge deglitch filter includes:
a third inverter including:
a third inverter input coupled to the data input; and
a third inverter output;

a fourth inverter including:
a fourth inverter input coupled to the third inverter output; and
a fourth inverter output;

a second resistor including:
a third resistor terminal; and
a fourth resistor terminal coupled to the fourth inverter output;

a second capacitor coupled between the third resistor terminal and the ground terminal;
a second switch coupled between the third resistor terminal and the ground terminal, the second switch including a second control input coupled to the third inverter output; and
a second Schmitt trigger circuit including:
an input coupled to the third resistor terminal; and
an output coupled to the set input of the latch circuitry.

4. The clock data recovery circuit of claim 1 , wherein the delayed pulse circuit includes:
a delay circuit including:
an input coupled to the input of the delayed pulse circuit; and
an output; and

a pulse generation circuit including:
an input coupled to the output of the delay circuit; and
an output coupled to the pulse output.

5. The clock data recovery circuit of claim 4 , wherein:
the delay circuit includes:
a first resistor including:
a first resistor terminal; and
a second resistor terminal coupled to the input of the delayed pulse circuit;

a first capacitor coupled between the first resistor terminal and a ground terminal;
a first Schmitt trigger circuit including:
an input coupled to the first resistor terminal; and
an output; and

the pulse generation circuit includes:
a second resistor including:
a third resistor terminal; and
a fourth resistor terminal coupled to the output of the first Schmitt trigger circuit;
a second capacitor coupled between the third resistor terminal and the ground terminal;

a second Schmitt trigger circuit including:
an input coupled to the third resistor terminal; and
an output;

a logic gate including:
a first input coupled to the output of the first Schmitt trigger circuit;
a second input coupled to the output of the second Schmitt trigger circuit; and
an output coupled to the pulse output.

6. The clock data recovery circuit of claim 1 , wherein the enable input is a first enable input, and the timer circuit includes:
an oscillator circuit including:
a second enable input coupled to the first enable input; and
a clock output; and

a cycle detection circuit including:
a clock input coupled to the clock output of the oscillator circuit;
a clear input coupled to the reset input; and
a cycle complete output coupled to the bit output.

7. The clock data recovery circuit of claim 6 , wherein the cycle detection circuit includes:
first latch circuitry including:
a first clock input coupled to the clock output of the oscillator circuit;
a first data input coupled to a voltage source terminal;
a first clear input coupled to the reset input; and
a first latch output;

second latch circuitry including:
a second clock input coupled to the clock output of the oscillator circuit;
a second data input;
a second clear input coupled to the reset input; and
a second latch output coupled to the bit output; and

a logic gate including:
a first input coupled to the first latch output;
a second input coupled to the second latch output; and
an output coupled to the second data input.

8. The clock data recovery circuit of claim 6 , wherein the reset input is a first reset input, and the oscillator circuit includes:
a first ramp circuit;
a first comparator including:
a first input coupled to the first ramp circuit;
a second input coupled to a voltage reference terminal; and
a first comparator output;

a second ramp circuit;
a second comparator including:
a first input coupled to the second ramp circuit;
a second input coupled to the voltage reference terminal; and
a second comparator output;

latch circuitry including:
a set input coupled the first comparator output;
a second reset input coupled to the second comparator output; and
an output coupled to the clock output of the oscillator circuit.

Assignees

• Texas Instruments Inc

Inventors

• Hanschke Michael Ryan
• Pandey Pankaj
• Pham Joseph
• Evans David Wayne

Classifications

• H04L7/0037

  Delay of clock signal · CPC title

• G06F2201/81

  Threshold · CPC title

• G06F11/1604 Primary

  where the fault affects the clock signals of a processing unit and the redundancy is at or within the level of clock signal generation hardware · CPC title

• H04L7/0041

  Delay of data signal · CPC title

• H04L7/0045

  Correction by a latch cascade · CPC title