Array substrate and manufacturing method thereof, display panel and backlight module

Patent metadata

Field	Value
Publication number	US-11990481-B2
Application number	US-202017418945-A
Country	US
Kind code	B2
Filing date	Sep 18, 2020
Priority date	Sep 18, 2020
Publication date	May 21, 2024
Grant date	May 21, 2024

Abstract

The present disclosure provides an array substrate and a manufacturing method thereof, a display panel and a backlight module. The manufacturing method of the array substrate includes: providing a base substrate; forming a metal wiring layer on a side of the base substrate, the metal wiring layer including a first copper metal layer; forming a planarization layer on a side of the metal wiring layer away from the base substrate; forming a drive lead layer on a side of the planarization layer away from the base substrate, the drive lead layer being electrically connected to the metal wiring layer, the drive lead layer including a second copper metal layer with a thickness larger than that of the first copper metal layer; forming a functional device layer on a side of the drive lead layer away from the base substrate.

First claim

What is claimed is:

1. An array substrate, comprising:
a base substrate;
a metal wiring layer provided on a side of the base substrate and comprising a first copper metal layer;
a planarization layer provided on a side of the metal wiring layer away from the base substrate;
a drive lead layer provided on a side of the planarization layer away from the base substrate, wherein the drive lead layer is electrically connected to the metal wiring layer, the drive lead layer comprises a second copper metal layer, and a thickness of the second copper metal layer is greater than a thickness of the first copper metal layer; and
a functional device layer provided on a side of the drive lead layer away from the base substrate, wherein the functional device layer is electrically connected to the metal wiring layer or the drive lead layer.

2. The array substrate according to claim 1 , wherein the metal wiring layer comprises a connection lead and a device pad electrically connected to the connection lead;
wherein the drive lead layer comprises a drive lead electrically connected to the connection lead.

3. The array substrate according to claim 1 , wherein the metal wiring layer comprises a connection lead;
wherein the drive lead layer comprises a drive lead and a device pad, and both the drive lead and the device pad are electrically connected to the connection lead.

4. A backlight module, comprising the array substrate according to claim 1 , wherein a functional device in the functional device layer is a micro light emitting diode or a mini light emitting diode.

5. A display panel, comprising the array substrate according to claim 1 , wherein a functional device in the functional device layer is a micro light emitting diode or a mini light emitting diode.

6. A method for manufacturing an array substrate, comprising:
providing a base substrate;
forming a metal wiring layer on a side of the base substrate, the metal wiring layer comprising a first copper metal layer;
forming a planarization layer on a side of the metal wiring layer away from the base substrate;
forming a drive lead layer on a side of the planarization layer away from the base substrate, wherein the drive lead layer is electrically connected to the metal wiring layer, the drive lead layer comprises a second copper metal layer, and a thickness of the second copper metal layer is greater than a thickness of the first copper metal layer; and
forming a functional device layer on a side of the drive lead layer away from the base substrate, wherein the functional device layer is electrically connected to the metal wiring layer or the drive lead layer.

7. The method for manufacturing the array substrate according to claim 6 , wherein forming the metal wiring layer on the side of the base substrate comprises: forming the metal wiring layer on the side of the base substrate, the metal wiring layer comprising a connection lead;
wherein forming the drive lead layer on the side of the planarization layer away from the base substrate comprises:
forming the drive lead layer on the side of the planarization layer away from the base substrate, wherein the drive lead layer comprises a drive lead and a device pad, and both the drive lead and the device pad are electrically connected to the connection lead.

8. The method for manufacturing the array substrate according to claim 7 , wherein forming the planarization layer on the side of the metal wiring layer away from the base substrate comprises:
forming the planarization layer on the side of the metal wiring layer away from the base substrate, wherein the planarization layer has a first via hole and a second via hole exposing the connection lead;
wherein forming the drive lead layer on the side of the planarization layer away from the base substrate comprises:
forming a seed metal layer on the side of the planarization layer away from the base substrate, wherein the seed metal layer comprises a device pad seed layer and a drive lead seed layer, the device pad seed layer is electrically connected to the connection lead through the first via hole, and the drive lead seed layer is electrically connected to the connection lead through the second via hole;
forming a copper growth layer on a side of the seed metal layer away from the base substrate using an electroless copper plating method, wherein the copper growth layer comprises a device pad growth layer on a surface of the device pad seed layer away from the base substrate and a drive lead growth layer on a surface of the drive lead seed layer away from the base substrate;
wherein the second copper metal layer comprises the copper growth layer and a copper seed layer in the seed metal layer.

9. The method for manufacturing the array substrate according to claim 6 , wherein forming the metal wiring layer on the side of the base substrate comprises: forming the metal wiring layer on the side of the base substrate, the metal wiring layer comprising a connection lead and a device pad electrically connected to the connection lead;
wherein forming the drive lead layer on the side of the planarization layer away from the base substrate comprises:
forming the drive lead layer on the side of the planarization layer away from the base substrate, wherein the drive lead layer comprises a drive lead electrically connected to the connection lead.

10. The method for manufacturing the array substrate according to claim 9 , wherein forming the drive lead layer on the side of the planarization layer away from the base substrate comprises:
forming a seed metal layer on the side of the planarization layer away from the base substrate, wherein the seed metal layer comprises a drive lead seed layer; and
forming a copper growth layer on a side of the seed metal layer away from the base substrate using a copper electroplating method, wherein the copper growth layer comprises a drive lead growth layer on a surface of the drive lead seed layer away from the base substrate, and wherein the second copper metal layer comprises the copper growth layer and a copper seed layer in the seed metal layer;
wherein forming the planarization layer on the side of the metal wiring layer away from the base substrate comprises:
forming a planarization precursor layer on the side of the metal wiring layer away from the base substrate, wherein the planarization precursor layer has a third via hole exposing the connection lead, so that the seed metal layer is electrically connected to the connection lead through the third via hole; and
after forming the seed metal layer, forming a fourth via hole on the planarization precursor layer, wherein the fourth via hole exposes the device pad.

11. The method for manufacturing the array substrate according to claim 10 , wherein forming the metal wiring layer on the side of the base substrate comprises:
forming the metal wiring layer on the side of the base substrate, wherein the metal wiring layer comprises the first copper metal layer and a protective metal layer arranged on a surface of the first copper metal layer away from the base substrate, and a material of the protective metal layer is nickel or copper-nickel alloy;
wherein forming the fourth via hole on the planarization precursor layer comprises:
after forming the seed metal layer and before forming the copper growth layer, forming the fourth via hole on the planarization precursor layer.

12. The method for manufacturing the array substrate according to claim 6 , wherein providing the base substrate comprises: providing a first motherboard substrate, wherein the first motherboard substrate comprises base substrates of a plurality of array substrates;
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Assignees

• Boe Technology Group Co Ltd

Inventors

• Cao Zhanfeng
• Wang Ke
• Liang Zhiwei
• Wang Jianguo
• Zhang Guocai
• Lu Xinhong
• Qi Qi

Classifications

• H10W90/00 Primary

  Package configurations · CPC title

• H10D86/0221

  comprising manufacture, treatment or patterning of TFT semiconductor bodies · CPC title

• H10D86/441

  Interconnections, e.g. scanning lines · CPC title

• H10H20/0364

  of interconnections · CPC title

• H10H29/142

  Two-dimensional arrangements, e.g. asymmetric LED layout · CPC title