Methods to fill high aspect ratio features on semiconductor substrates with mocvd cobalt film
US-2018151424-A1 · May 31, 2018 · US
US10177030B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-10177030-B2 |
| Application number | US-201715403667-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jan 11, 2017 |
| Priority date | Jan 11, 2017 |
| Publication date | Jan 8, 2019 |
| Grant date | Jan 8, 2019 |
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Methods and structures for forming cobalt contact and/or cobalt interconnects includes depositing a stress control layer onto the cobalt layer prior to annealing after which the stress control layer can be removed. The stress control layer prevents formation of defects that can occur in the absence of the stress control layer.
Opening claim text (preview).
What is claimed is: 1. An intermediate semiconductor structure, comprising: a patterned interlayer dielectric overlaying a semiconductor substrate, wherein the patterned interlayer dielectric comprises at least one opening extending through the interlayer dielectric to the semiconductor substrate; a cobalt metal filling the at least one opening; and a stress control layer on top of the cobalt metal filling, wherein the cobalt metal filling is substantially void free subsequent to an annealing process with the stress control layer on top of the cobalt metal filling wherein an aspect ratio of a height and a width of the at least one opening is at least about 10:1.
the principal metal being a transition metal · CPC title
based on metals, e.g. alloys, metal silicides (H10W20/4484 takes precedence) · CPC title
using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title
by forming openings in the dielectric parts · CPC title
by modifying the conductivity of conductive parts, e.g. by alloying · CPC title
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