Semiconductor package

Patent metadata

Field	Value
Publication number	US-11990452-B2
Application number	US-202318120587-A
Country	US
Kind code	B2
Filing date	Mar 13, 2023
Priority date	Jul 13, 2020
Publication date	May 21, 2024
Grant date	May 21, 2024

Abstract

A semiconductor package includes a first semiconductor chip comprising a semiconductor substrate and a redistribution pattern on a top surface of the semiconductor substrate, the redistribution pattern having a hole exposing an inner sidewall of the redistribution pattern, a second semiconductor chip on a top surface of the first semiconductor chip, and a bump structure disposed between the first semiconductor chip and the second semiconductor chip. The bump structure is disposed in the hole and is in contact with the inner sidewall of the redistribution pattern.

First claim

What is claimed is:

1. A semiconductor package comprising:
a first semiconductor chip comprising a semiconductor substrate and a redistribution pattern on a top surface of the semiconductor substrate, the redistribution pattern having a hole exposing an inner sidewall of the redistribution pattern;
a second semiconductor chip on a top surface of the first semiconductor chip; and
a bump structure disposed between the first semiconductor chip and the second semiconductor chip,
wherein the bump structure comprises a solder pattern filling the hole and being in direct contact with the inner sidewall of the redistribution pattern,
wherein a distance between the first and second semiconductor chips is less than a height of the bump structure,
wherein the distance between the first and second semiconductor chips ranges from about 3 μm to about 20 μm, and
wherein the height of the bump structure ranges from about 5 μm to about 30 μm.

2. The semiconductor package of claim 1 ,
wherein the first semiconductor chip further comprises a protective layer disposed on the redistribution pattern and having an opening, and
wherein the opening is connected to the hole and exposes an inner sidewall of the protective layer.

3. The semiconductor package of claim 2 , wherein the solder pattern covers the inner sidewall of the protective layer.

4. The semiconductor package of claim 2 , wherein a distance between a top surface of the protective layer and a bottom surface of the hole ranges from ab out 2 μm to ab out 10 μm.

5. The semiconductor package of claim 2 , wherein the bump structure further comprises a pillar pattern disposed between the solder pattern and a chip pad of the second semiconductor chip.

6. The semiconductor package of claim 5 , wherein a bottom surface of the pillar pattern is disposed at a lower level than a top surface of the protective layer.

7. The semiconductor package of claim 1 , further comprising:
an underfill layer disposed in a gap region between the first and second semiconductor chips and covering the bump structure.

8. The semiconductor package of claim 7 , wherein a thickness of the underfill layer is less than a height of the bump structure.

9. The semiconductor package of claim 7 , wherein the underfill layer has a thermal conductivity lower than a thermal conductivity of the bump structure.

10. A semiconductor package comprising:
a first semiconductor chip comprising a semiconductor substrate, an insulating layer on the semiconductor substrate, and a redistribution pattern on the insulating layer, the redistribution pattern having a hole exposing an inner sidewall of the redistribution pattern;
a second semiconductor chip on a top surface of the first semiconductor chip; and
a bump structure disposed between the first semiconductor chip and the second semiconductor chip,
wherein the bump structure comprises a solder pattern filling the hole and being in direct contact with the inner sidewall of the redistribution pattern,
wherein a bottom surface of the hole is provided in the redistribution pattern,
wherein a bottom surface and a sidewall of the solder pattern are in contact with the redistribution pattern, and
wherein the bottom surface of the solder pattern is spaced apart from the insulating layer.

11. The semiconductor package of claim 10 , wherein the bottom surface of the solder pattern is disposed at a higher level than a bottom surface of the redistribution pattern.

12. The semiconductor package of claim 10 ,
wherein the first semiconductor chip further comprises a through-structure in the semiconductor substrate, and
wherein the redistribution pattern is electrically connected to the through-structure.

13. The semiconductor package of claim 12 , wherein the bump structure is spaced apart from the through-structure when viewed in a plan view.

14. The semiconductor package of claim 10 ,
wherein the first semiconductor chip further comprises a protective layer disposed on the redistribution pattern and having an opening, and
wherein a width of the opening is greater than a width of the hole.

15. The semiconductor package of claim 14 , wherein the sidewall of the solder pattern has a stepped shape.

16. A semiconductor package comprising:
a first semiconductor chip comprising a semiconductor substrate, a lower redistribution pattern, a lower protective layer, and an upper redistribution pattern sequentially stacked;
a second semiconductor chip on a top surface of the first semiconductor chip;
a solder pattern in direct contact with an inner sidewall of the lower redistribution pattern, an inner sidewall of the lower protective layer and an inner sidewall of the upper redistribution pattern; and
a pillar pattern disposed between the solder pattern and the second semiconductor chip,
wherein the solder pattern has a horizontal width that decreases from an upper surface of the upper redistribution pattern toward an upper surface of the semiconductor substrate.

17. The semiconductor package of claim 16 ,
wherein the lower redistribution pattern has a lower hole, the lower protective layer has a lower opening, and the upper redistribution pattern has an upper hole, and
wherein the lower hole, the lower opening, and the upper hole are connected to each other.

18. The semiconductor package of claim 17 , wherein the solder pattern is disposed in the lower hole, the lower opening, and the upper hole.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Namhoon
• Jo Chajea
• Kwon Ohguk
• Kim Hyoeun
• Yeon Seunghoon

Classifications

• H10W20/2134

  TSVs extending from the semiconductor wafer into back-end-of-line layers · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W90/26

  the stacked chips being of the same size without any chips being laterally offset, e.g. chip stacks having a rectangular shape · CPC title

• H10W90/20

  Configurations of stacked chips · CPC title

• H10W74/15

  on active surfaces of flip-chip devices, e.g. underfills · CPC title