Method for an internal command from a plurality of processing cores with memory sub-system that cache identifiers for access commands

Patent metadata

Field	Value
Publication number	US-11989600-B2
Application number	US-202217945673-A
Country	US
Kind code	B2
Filing date	Sep 15, 2022
Priority date	Apr 7, 2020
Publication date	May 21, 2024
Grant date	May 21, 2024

Abstract

Methods, systems, and devices for caching identifiers for access commands are described. A memory sub-system can receive an access command to perform an access operation on a transfer unit of the memory sub-system. The memory sub-system can store an identifier associated with the access command in a memory component and can generate an internal command using a first core of the memory sub-system. In some embodiments, the memory sub-system can store the identifier in a shared memory that is accessible by the first core and can issue the internal command to perform the access operation on the memory sub-system.

First claim

What is claimed is:

1. A method, comprising:
receiving an access command to perform an access operation on a transfer unit of a memory sub-system;
storing an identifier associated with the access command;
storing the identifier associated with an internal command in a shared memory that is accessible by a plurality of cores; and
issuing the internal command to perform the access operation on the memory sub-system.

2. The method of claim 1 , further comprising:
receiving the identifier based at least in part on performing the access operation on the memory sub-system; and
determining whether the access operation was completed based at least in part on receiving the identifier.

3. The method of claim 2 , further comprising:
reading a command entry comprising the identifier from a queue based at least in part on determining that the access operation was not completed; and
updating the internal command based at least in part on reading the command entry from the queue.

4. A method, comprising:
receiving an access command to perform an access operation on a transfer unit of a memory sub-system;
receiving an identifier based at least in part on performing the access operation on the memory sub-system;
allocating the identifier to the access command based at least in part on receiving the access command;
storing the identifier associated with the access command;
determining whether the access operation was completed based at least in part on receiving the identifier;
reading a command entry comprising the identifier from a queue based at least in part on determining that the access operation was not completed;
updating an internal command based at least in part on reading the command entry from the queue;
storing the identifier associated with the internal command;
issuing the internal command to perform the access operation on the memory sub-system;
determining that an entry of the memory sub-system comprises the identifier; and
reading the entry comprising the identifier based at least in part on determining that the command entry comprises the identifier.

5. The method of claim 2 , further comprising:
identifying a status associated with the access command, based at least in part on determining that the access operation was not completed; and
comparing the status to the identifier, wherein the identifier associated with the internal command remains stored based on comparing the status to the identifier.

6. The method of claim 1 , further comprising:
determining, by a coherency checker, whether the identifier matches one or more other identifiers based at least in part on issuing the internal command.

7. The method of claim 6 , further comprising:
storing, at a system memory, the identifier associated with the access command based at least in part on the identifier not matching one or more other identifiers stored in the system memory.

8. The method of claim 1 , further comprising:
receiving, by a component of the memory sub-system, the internal command; and
performing, via component of the memory sub-system, the access operation on the memory sub-system based in part on receiving the internal command.

9. A non-transitory computer-readable medium storing code, the code comprising instructions executable by a processor to:
receive an access command to perform an access operation on a transfer unit of a memory sub-system;
store an identifier associated with the access command;
store the identifier associated with an internal command in a shared memory that is accessible by a plurality of cores; and
issue the internal command to perform the access operation on the memory sub-system.

10. The non-transitory computer-readable medium of claim 9 , wherein the instructions are further executable by the processor to:
receive the identifier based at least in part on performing the access operation on the memory sub-system; and
determine whether the access operation was completed based at least in part on receiving the identifier.

11. The non-transitory computer-readable medium of claim 10 , wherein the instructions are further executable by the processor to:
read a command entry comprising the identifier from a queue based at least in part on determining that the access operation was not completed; and
update the internal command based at least in part on reading the command entry from the queue.

12. A non-transitory computer-readable medium storing code, the code comprising instructions executable by a processor to:
receive an access command to perform an access operation on a transfer unit of a memory sub-system;
receive an identifier based at least in part on performing the access operation on the memory sub-system;
allocate the identifier to the access command based at least in part on receiving the access command;
store the identifier associated with the access command;
determine whether the access operation was completed based at least in part on receiving the identifier;
read a command entry comprising the identifier from a queue based at least in part on determining that the access operation was not completed;
update an internal command based at least in part on reading the command entry from the queue;
store the identifier associated with the internal command;
issue the internal command to perform the access operation on the memory sub-system;
determine that an entry of the memory sub-system comprises the identifier; and
read the entry comprising the identifier based at least in part on determining that the command entry comprises the identifier.

13. The non-transitory computer-readable medium of claim 10 , wherein the instructions are further executable by the processor to:
identify a status associated with the access command, based at least in part on determining that the access operation was not completed; and
compare the status to the identifier, wherein the identifier associated with the internal command remains stored based on comparing the status to the identifier.

14. The non-transitory computer-readable medium of claim 9 , wherein the instructions are further executable by the processor to:
determine, by a coherency checker, whether the identifier matches one or more other identifiers based at least in part on issuing the internal command.

15. The non-transitory computer-readable medium of claim 14 , wherein the instructions are further executable by the processor to:
store, at a system memory, the identifier associated with the access command based at least in part on the identifier not matching one or more other identifiers stored in the system memory.

16. The non-transitory computer-readable medium of claim 9 , wherein the instructions are further executable by the processor to:
receive, by a component of the memory sub-system, the internal command; and
perform, via component of the memory sub-system, the access operation on the memory sub-system based in part on receiving the internal command.

17. An apparatus, comprising: a controller associated with a memory device, wherein the controller is configured to cause the apparatus to:
receive an access command to perform an access operation on a transfer unit of a memory sub-system;
store an identifier associated with the access command;
store the identifier associated with an internal command in a shared memory that is accessible by a plurality of cores; and
issue the internal command to perform the access operation on the memory sub-system.

18. The apparatus of claim 17 , wherein the controller is further config

Assignees

• Micron Technology Inc

Inventors

• Traver John
• Shoen Jay R

Classifications

• G06F9/544 Primary

  Buffers; Shared memory; Pipes · CPC title

• G06F9/3836

  Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution · CPC title

• G06F9/546

  Message passing systems or structures, e.g. queues · CPC title

• G06F12/0246

  in block erasable memory, e.g. flash memory · CPC title

• G06F12/084

  with a shared cache · CPC title