Method of manufacturing MRAM device with enhanced etch control

Patent metadata

Field	Value
Publication number	US-11985904-B2
Application number	US-202117168974-A
Country	US
Kind code	B2
Filing date	Feb 5, 2021
Priority date	Apr 22, 2020
Publication date	May 14, 2024
Grant date	May 14, 2024

Abstract

A method of manufacturing a semiconductor device includes: providing a substrate, the substrate defining a logic region and a memory region; depositing a bottom electrode layer across the logic region and the memory region; depositing a magnetic tunnel junction (MTJ) layer over the bottom electrode layer; depositing a first conductive layer over the MTJ layer; depositing a sacrificial layer over the first conductive layer; etching the sacrificial layer in the memory region to expose the first conductive layer in the memory region while keeping the first conductive layer in the logic region covered; depositing a second conductive layer in the memory region and the logic region; patterning the second conductive layer to expose the MTJ layer in the memory region; and etching the patterned second conductive layer and the MTJ layer to form a top electrode and an MTJ, respectively, in the memory region.

First claim

What is claimed is:

1. A method of manufacturing a semiconductor device, comprising:
providing a substrate, the substrate comprising a logic region and a memory region;
depositing a bottom electrode layer across the logic region and the memory region;
depositing a magnetic tunnel junction (MTJ) layer over the bottom electrode layer;
depositing a first conductive layer over the MTJ layer;
depositing a sacrificial layer over the first conductive layer;
removing the sacrificial layer in the memory region to expose the first conductive layer in the memory region, while leaving the sacrificial layer in the logic region as a cover layer to protect the first conductive layer in the logic region;
after the sacrificial layer is removed, depositing a second conductive layer in the memory region and the logic region;
patterning the second conductive layer to expose the MTJ layer in the memory region, while protecting the first conductive layer and the MTJ layer by the cover layer in the logic region by the cover layer; and
etching the patterned second conductive layer and the MTJ layer to form a top electrode and an MTJ, respectively, in the memory region.

2. The method according to claim 1 , further comprising, prior to the depositing of the bottom electrode layer:
forming a metal line layer having a metal line;
depositing a first dielectric layer in the memory region and the logic region over the metal line layer; and
forming a bottom electrode via within the first dielectric layer in the memory region.

3. The method according to claim 2 , wherein etching the patterned second conductive layer and the MTJ layer to form a top electrode and an MTJ, respectively, in the memory region comprises reducing a thickness of the first dielectric layer in the logic region.

4. The method according to claim 3 , wherein the metal line is covered by the first dielectric region in the logic region upon completion of etching the thickness of the first dielectric layer.

5. The method according to claim 1 , wherein patterning the second conductive layer to expose the MTJ layer in the memory region comprises removing the second conductive layer in the logic region.

6. The method according to claim 1 , further comprising depositing a mask layer over the second conductive layer, wherein patterning the second conductive layer to expose the MTJ layer in the memory region comprises patterning the mask layer, and wherein the second conductive layer is patterned using the patterned mask layer as an etch mask.

7. The method according to claim 6 , wherein the mask layer comprises a same material as a material in the sacrificial layer.

8. The method according to claim 6 , wherein etching the patterned second conductive layer and the MTJ layer to form a top electrode and an MTJ, respectively, in the memory region comprises performing an ion bombardment etching to remove an entirety of the mask layer and a portion of the second conductive layer in the memory region.

9. The method according to claim 8 , wherein the ion bombardment etching etches the MTJ layer using at least the second conductive layer as an etch mask to form the MTJ in the memory region.

10. The method according to claim 9 , wherein the ion bombardment etching further etches the bottom electrode layer using the second conductive layer as an etch mask to form a bottom electrode.

11. The method according to claim 8 , wherein the ion bombardment etching removes the mask layer and the second conductive layer in the logic region.

12. The method according to claim 1 , further comprising forming a spacer laterally surrounding sidewalls of the top electrode and the MTJ.

13. A method of manufacturing a semiconductor device, comprising:
forming a substrate, the substrate comprising a logic region and a memory region;
depositing a bottom electrode layer and a magnetic tunnel junction (MTJ) layer over the substrate;
depositing a first conductive layer over the MTJ layer;
depositing an etch buffer layer over the first conductive layer;
removing the etch buffer layer in the memory region to expose the first conductive layer in the memory region, while leaving the etch buffer layer in the logic region as a cover layer to protect the first conductive layer in the logic region;
after the etch buffer layer is removed, depositing a second conductive layer over the first conductive layer in the memory region and over the cover layer in the logic region, respectively;
depositing a mask layer over the second conductive layer;
patterning the mask layer to form a pattern of a top electrode in the memory region;
patterning the first and second conductive layers by transferring the pattern to the first and second conductive layers;
etching the mask layer, the patterned first and second conductive layers, the MTJ layer and the bottom electrode layer using an etching operation to form the top electrode, an MTJ and a bottom electrode in the memory region;
removing the cover layer from the logic region; and
removing the bottom electrode layer, the MTJ layer and the first conductive layer from the logic region,
wherein during the patterning the first and second conductive layers and during the removing the cover layer from the logic region, no cover layer exists in the memory region.

14. The method according to claim 13 , wherein patterning the first and second conductive layers comprises removing the second conductive layer in the logic region.

15. The method according to claim 13 , wherein the first conductive layer comprises a same conductive material as a conductive material in the second conductive layer.

16. The method according to claim 13 , further comprising causing an interface layer to be grown on the first conductive layer prior to the depositing of the second conductive layer.

17. The method according to claim 13 , further comprising, prior to the depositing of the bottom electrode layer:
forming a dielectric layer across the memory region and the logic region over the substrate; and
forming a bottom electrode via within the dielectric layer, wherein the bottom electrode layer is electrically connected to the bottom electrode via,
wherein the etching operation stops at the dielectric layer in the memory region while removing a thickness of the dielectric layer in the logic region.

18. The method according to claim 17 , further comprising completely removing the dielectric layer in the logic region subsequent to the etching operation.

19. A method of manufacturing a semiconductor device, comprising:
forming an electrode pattern over a substrate embedded in an insulating layer, the substrate comprising a logic region and a memory region, the electrode pattern being disposed in the memory region;
depositing a bottom electrode layer across the logic region and the memory region to contact the electrode pattern;
depositing a magnetic tunnel junction (MTJ) layer over the bottom electrode layer;
depositing a first conductive layer over the MTJ layer;
depositing a sacrificial layer over the first conductive layer;
removing the sacrificial layer in the memory region to expose the first conductive layer above the electrode pattern and the insulating layer in the memory region, while keeping the first conductive layer in the logic region covered by a cover layer;
after the sacrificial layer is removed, depositing a second conductive layer in the memory region and the logic region;
patterning the second conductive layer to expose the MTJ layer in the memory region, while protecting the first conduc

Assignees

• Taiwan Semiconductor Mfg Co Ltd
• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chien Yu-Jen
• Wu Jung-Tang
• Wu Szu-Hua
• Lee Chin-Szu
• Wu Meng-Yu

Classifications

• H10N50/01 Primary

  Manufacture or treatment · CPC title

• H10B61/22 Primary

  of the field-effect transistor [FET] type · CPC title

• H10N50/80

  Constructional details · CPC title

• H10N50/10

  Magnetoresistive devices · CPC title