Vertical 2-transistor memory cell

Patent metadata

Field	Value
Publication number	US-11985806-B2
Application number	US-201916721380-A
Country	US
Kind code	B2
Filing date	Dec 19, 2019
Priority date	Dec 26, 2018
Publication date	May 14, 2024
Grant date	May 14, 2024

Abstract

Some embodiments include apparatuses and methods of forming the apparatus. One of the apparatuses and methods includes a memory cell having a first transistor and a second transistor located over a substrate. The first transistor includes a channel region. The second transistor includes a channel region located over the channel region of the first transistor and electrically separated from the first channel region. The memory cell includes a memory element located on at least one side of the channel region of the first transistor. The memory element is electrically separated from the channel region of the first transistor, and electrically coupled to the channel of the second transistor.

First claim

What is claimed is:

1. A method comprising:
forming a first transistor of a memory cell over a substrate, including forming a channel region of the first transistor;
forming a memory element of the memory cell on at least one side of the channel region of the first transistor, such that the memory element is separated from the channel region of the first transistor by a dielectric material; and
forming a second transistor of the memory cell, including forming a channel region of the second transistor, such that the channel region of the second transistor is coupled to the memory element.

2. The method of claim 1 , wherein forming the memory element includes:
forming a first portion of the memory element on a first side of the channel region of the first transistor; and
forming a second portion of the memory element on a second side of the channel region of the first transistor.

3. The method of claim 1 , further comprising:
forming a conductive coupling, such that the conductive coupling contacts the channel region of the second transistor and the memory element.

4. The method of claim 3 , wherein forming the conductive coupling includes:
forming a first portion of the conductive coupling, such that the first portion of the conductive coupling contacts the channel region of the second transistor and contacts a first portion of the memory element; and
forming a second portion of the conductive coupling, such that the second portion of the conductive coupling contacts the channel region of the second transistor and contacts a second portion of the memory element.

5. The method of claim 1 , wherein the memory element includes poly silicon.

6. The method of claim 1 , wherein the channel region of the first transistor includes polysilicon.

7. The method of claim 1 , wherein the second material includes an oxide material.

8. The method of claim 1 , wherein the second material includes at least one of zinc tin oxide (ZTO), indium zinc oxide (IZO), zinc oxide (ZnO x ), indium gallium zinc oxide (IGZO), indium gallium silicon oxide (IGSO), indium oxide (InO x , In 2 O 3 ), tin oxide (SnO 2 ), titanium oxide (TiOx), zinc oxide nitride (Zn x O y N z ), magnesium zinc oxide (Mg x Zn y O z ), indium zinc oxide (In x Zn y O z ), indium gallium zinc oxide (In x Ga y Zn z O a ), zirconium indium zinc oxide (Zr x In y Zn z O a ), hafnium indium zinc oxide (Hf x In y Zn z O a ), tin indium zinc oxide (Sn x In y Zn z O a ), aluminum tin indium zinc oxide (Al x Sn y In z Zn a O d ), silicon indium zinc oxide (Si x In y Zn z O a ), zinc tin oxide (Zn x Sn y O z ), aluminum zinc tin oxide (Al x Zn y Sn z O a ), gallium zinc tin oxide (Ga x Zn y Sn z O a ), zirconium zinc tin oxide (Zr x Zn y Sn z O a ), and indium gallium silicon oxide (InGaSiO).

9. The method of claim 1 , further comprising:
forming a first data line between the channel region of the first transistor and the substrate; and
forming a second data line over the channel region of the first transistor, such that the channel region of the first transistor contacts the first and second data lines.

10. The method of claim 9 , further comprising:
forming a third data line over the channel region of the second transistor and contacting the second material.

11. A method comprising:
forming a memory cell over a substrate, including forming a first transistor of the memory cell over a substrate and forming a second transistor of the memory cell over the first transistor, the first transistor including a first material, and the second transistor including a second material formed over the first material of the first transistor;
forming a first conductive line having a portion adjacent a first side of the first material;
forming a first additional conductive line having a portion adjacent a second side of the first material;
forming a second conductive line having a portion adjacent a first side of the second material; and
forming a second additional conductive line having a portion adjacent a second side of the second material.

12. The method of claim 11 , further comprising:
forming a third conductive line over the substrate and between the first transistor and the substrate, wherein the third conductive line has length in a first direction, and each of the first, first additional, second, and second additional conductive lines has a length in a second direction.

13. The method of claim 11 , wherein forming the memory cell includes forming a memory element of the memory cell, wherein the first and second sides of the first material are opposite from each other in a first direction, the memory element includes first portion adjacent a third side of the first material, and a second portion adjacent a fourth side of the first material, and the third and fourth sides of the first material are opposite from each other in a second direction.

14. The method of claim 11 , wherein the second material includes gallium phosphide (GaP).

15. The method of claim 11 , wherein the first material includes one of poly silicon and metal.

16. The method of claim 11 , further comprising:
forming a first conductive connection, such that the first conductive connection is coupled to the first conductive line and the first additional conductive line; and
forming a second conductive connection, such that the second conductive connection is coupled to the second conductive line and the second additional conductive line.

17. The method of claim 11 , further comprising:
forming a third conductive connection, such that the third conductive connection is coupled to the first, first additional, second, and second additional conductive lines.

18. A method comprising:
forming a conductive region over substrate;
forming a first memory cell over the conductive region, including forming a first transistor of the first memory cell and forming a second transistor of the first cell over the first transistor of the first memory cell;
forming a second memory cell over the conductive region, including forming a first transistor of the second memory cell and forming a second transistor of the second memory cell over the first transistor of second memory cell;
forming a third memory cell over the conductive region, including forming a first transistor of the third memory cell and forming a second transistor of the third memory cell over the first transistor of third memory cell;
forming a first conductive structure between the first and second memory cells, the first conductive structure contacting the conductive region; and
forming a second conductive structure between the second and third memory cells, the second conductive structure contacting the conductive region.

19. The method of claim 18 , further comprising:
forming a memory element of each of the first, second, and third memory cells, such that:
the first conductive structure is adjacent a first portion of the memory element of the first memory cell and adjacent a portion of the memory element of the second memory cell; and
the second conductive structure is adjacent a second portion of the memory element of the first memory cell and adjacent a portion of the memory element of the third memory cell.

20. The method of claim 18 , further comprising:
forming a first conductive line, such that the first conductive line includes:
a first portion adjacent a side of the first transistor of the first memory cell;
a second portion adjacent a side of the first transistor of the second memory cell; and
a third portion adjacent a s

Assignees

• Micron Technology Inc

Inventors

• Karda Kamal M
• Pulugurtha Srinivas
• Liu Haitao
• Sarpatwari Karthik
• Ramaswamy Durai Vishak Nirmal

Classifications

• H10B12/01 Primary

  Manufacture or treatment · CPC title

• G11C11/4023

  using field effect transistors · CPC title

• H10B12/20 Primary

  DRAM devices comprising floating-body transistors, e.g. floating-body cells · CPC title

• G11C11/403

  with charge regeneration common to a multiplicity of memory cells, i.e. external refresh · CPC title