Formation method of semiconductor structure

Patent metadata

Field	Value
Publication number	US-11984352-B2
Application number	US-202117480326-A
Country	US
Kind code	B2
Filing date	Sep 21, 2021
Priority date	Oct 27, 2020
Publication date	May 14, 2024
Grant date	May 14, 2024

Abstract

Provided is a formation method of a semiconductor structure, including: providing a substrate having a first region and a second region, a plurality of discrete through holes being formed in the substrate, an arrangement density of the through holes in the first region being greater than that in the second region; forming a sacrificial layer filling the through holes; etching some thickness of the substrate around the sacrificial layer to form openings, the openings surrounding the sacrificial layer, a depth of the opening being less than a depth of the through hole in a direction perpendicular to a surface of the substrate; and removing the sacrificial layer, the openings communicating with the corresponding through holes to form trenches.

First claim

What is claimed is:

1. A formation method of a semiconductor structure, comprising:
providing a substrate having a first region and a second region, a plurality of discrete through holes being formed in the substrate, an arrangement density of the through holes in the first region being greater than that in the second region;
forming a sacrificial layer filling the through holes;
etching some thickness of the substrate around the sacrificial layer to form openings, the openings surrounding the sacrificial layer, a depth of the openings being less than a depth of the through holes in a direction perpendicular to a surface of the substrate; and
removing the sacrificial layer, the openings communicating with the corresponding through holes to form trenches,
wherein the lower the arrangement density of the through holes, the deeper the correspondingly formed opening around the through hole.

2. The formation method of a semiconductor structure according to claim 1 , wherein in the direction perpendicular to the surface of the substrate, the sacrificial layer in the first region is flush with the sacrificial layer in the second region; the forming the sacrificial layer filling the through holes comprises the following steps:
forming a sacrificial film filling the through holes and covering the substrate; and
planarizing the sacrificial film, the remaining sacrificial film serving as the sacrificial layer.

3. The formation method of a semiconductor structure according to claim 2 , wherein the sacrificial film is planarized until a top surface of the remaining sacrificial film is parallel to a top surface of the substrate.

4. The formation method of a semiconductor structure according to claim 3 , wherein the planarization is carried out by chemical mechanical polish (CMP).

5. The formation method of a semiconductor structure according to claim 2 , wherein the sacrificial film is planarized until a top surface of the substrate is exposed.

6. The formation method of a semiconductor structure according to claim 5 , wherein the planarization is carried out by chemical mechanical polish (CMP).

7. The formation method of a semiconductor structure according to claim 2 , wherein a material of the sacrificial film comprises polysilicon.

8. The formation method of a semiconductor structure according to claim 1 , wherein the sacrificial layer is configured as a hard mask formed by spin coating.

9. The formation method of a semiconductor structure according to claim 8 , wherein the sacrificial layer is removed by using hydrogen plasma.

10. The formation method of a semiconductor structure according to claim 1 , wherein in a direction parallel to the surface of the substrate, a width of the opening in the second region is greater than a width of the opening in the first region.

11. The formation method of a semiconductor structure according to claim 1 , wherein the etching some thickness of the substrate around the sacrificial layer to form the openings comprises:
forming a patterned mask layer on a top surface of the substrate, in a direction parallel to the surface of the substrate, an orthographic projection of a pattern exposed by the patterned mask layer on the substrate completely covering an orthographic projection of the sacrificial layer on the substrate;
based on the patterned mask layer, etching some height of the substrate to form the openings; and
removing the patterned mask layer.

12. The formation method of a semiconductor structure according to claim 11 , wherein the forming the patterned mask layer on the top surface of the substrate comprises the following steps;
forming a mask layer on a top surface of the sacrificial layer;
forming a patterned photoresist on a top surface of the mask layer, an orthographic projection of the pattern, exposed by the patterned photoresist, on the substrate completely covering the orthographic projection of the sacrificial layer on the substrate; and
based on the patterned photoresist, etching part of the mask layer to form the patterned mask layer.

Assignees

• Changxin Memory Tech Inc

Inventors

• Xia Jun
• Bai Shijie

Classifications

• H10W20/0765

  the thin functional dielectric layers being temporary, e.g. sacrificial layers · CPC title

• H10W20/089

  using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title

• H10W20/01

  Manufacture or treatment · CPC title

• H10W20/0884

  involving forming vias by burying sacrificial pillars in the dielectric parts and removing the pillars · CPC title