Method and system for adjusting memory, and semiconductor device

Patent metadata

Field	Value
Publication number	US-11984190-B2
Application number	US-202117510453-A
Country	US
Kind code	B2
Filing date	Oct 26, 2021
Priority date	Aug 27, 2020
Publication date	May 14, 2024
Grant date	May 14, 2024

Abstract

Embodiments of the disclosure, there is provided a method, a system for adjusting the memory, and a semiconductor device. The method for adjusting the memory includes: acquiring a mapping relationship between a temperature of a transistor, an equivalent width-length ratio of a sense amplifier transistor in a sense amplifier and an actual time at which the data is written into the memory; acquiring a current temperature of the transistor; and adjusting the equivalent width-length ratio, based on the current temperature and the mapping relationship, so that the actual time at which the data is written into the memory corresponding to the adjusted equivalent width-length ratio is within a preset writing time.

First claim

The invention claimed is:

1. A method for adjusting a memory, wherein the memory comprises a transistor, a gate of the transistor is electrically connected with a Word Line (WL) of the memory, one of a source and a drain of the transistor is electrically connected with a Bit Line (BL) of the memory through a sense amplifier, and another one of the source and the drain of the transistor is electrically connected with a storage capacitor of the memory, the method comprising:
acquiring a mapping relationship between a temperature of the transistor, an equivalent width-length ratio of a sense amplifier transistor in the sense amplifier, and an actual time at which data is written into the memory;
acquiring a current temperature of the transistor; and
adjusting the equivalent width-length ratio, based on the current temperature and the mapping relationship, so that the actual time at which the data is written into the memory corresponding to the adjusted equivalent width-length ratio is within a preset writing time.

2. The method for adjusting the memory of claim 1 , wherein adjusting the equivalent width-length ratio, based on the current temperature and the mapping relationship comprises:
acquiring a preset temperature corresponding to the preset writing time;
acquiring a temperature difference between the current temperature and the preset temperature; and
adjusting the equivalent width-length ratio, according to the temperature difference and the mapping relationship.

3. The method for adjusting the memory of claim 2 , wherein before adjusting the equivalent width-length ratio, according to the temperature difference and the mapping relationship, the method further comprises:
determining whether the temperature difference exceeds a preset range; and
in response to the temperature difference exceeding the preset range, adjusting the equivalent width-length ratio according to the temperature difference and the mapping relationship.

4. The method for adjusting the memory of claim 2 , wherein adjusting the equivalent width-length ratio, according to the temperature difference and the mapping relationship comprises:
acquiring, according to the mapping relationship, a time difference between the actual time at which the data is written into the memory corresponding to the current temperature and the preset writing time; and
adjusting, according to the mapping relationship and the time difference, the equivalent width-length ratio to offset the time difference.

5. The method for adjusting the memory of claim 3 , wherein the preset range comprises a first preset range and a second preset range, and the second preset range is greater than the first preset range;
in response to the temperature difference exceeding the first preset range and not exceeding the second preset range, increasing or decreasing the equivalent width-length ratio, by a first preset value; and
in response to the temperature difference exceeding the second preset range, increasing or decreasing the equivalent width-length ratio by a second preset value, wherein the second preset value is greater than the first preset value.

6. The method for adjusting the memory of claim 1 , wherein acquiring the mapping relationship between the temperature of the transistor, the equivalent width-length ratio of the sense amplifier transistor in the sense amplifier, and the actual time at which the data is written into the memory comprises:
acquiring a first mapping relationship between the temperature of the transistor and the actual time at which the data is written into the memory;
acquiring a second mapping relationship between the equivalent width-length ratio of the sense amplifier transistor in the sense amplifier and the actual time at which the data is written into the memory; and
acquiring, based on the first mapping relationship and the second mapping relationship, the mapping relationship between the temperature of the transistor, the equivalent width-length ratio of the sense amplifier transistor in the sense amplifier, and the actual time at which the data is written into the memory.

7. The method for adjusting the memory of claim 1 , wherein the sense amplifier transistor comprises an array of sense amplifier transistors arranged in parallel,
and adjusting the equivalent width-length ratio comprising: adjusting the equivalent width-length ratio of the sense amplifier transistor in the sense amplifier by adjusting a number of the sense amplifier transistors in the array connected to the sense amplifier.

8. A system for adjusting a memory, wherein the system is applied to the memory, the system comprising:
a first acquisition circuit, configured to acquire a mapping relationship between a temperature of a transistor, an equivalent width-length ratio of a sense amplifier transistor in a sense amplifier, and an actual time at which data is written into the memory;
a second acquisition circuit, configured to acquire a current temperature of the transistor;
a processing circuit, configured to acquire an adjustment mode of the equivalent width-length ratio, based on the current temperature and the mapping relationship; and
an adjusting circuit, configured to adjust the equivalent width-length ratio, based on the adjustment mode, so that the actual time at which the data is written into the memory corresponding to the adjusted equivalent width-length ratio is within a preset writing time.

9. The system for adjusting the memory of claim 8 , wherein the second acquisition circuit comprises a temperature sensor arranged in the memory.

10. The system for adjusting the memory of claim 8 , wherein the processing circuit comprises:
a comparison circuit, configured to acquire a preset temperature corresponding to the preset writing time, and acquire a temperature difference between the current temperature and the preset temperature; and
a processing circuit, configured to acquire an adjustment mode of the equivalent width-length ratio, according to the temperature difference and the mapping relationship.

11. The system for adjusting the memory of claim 10 , wherein the processing circuit further comprises: a determination circuit, configured to determine whether the temperature difference exceeds a preset range; and
in response to the temperature difference exceeding the preset range, the processing circuit is configured to acquire the adjustment mode of the equivalent width-length ratio, according to the temperature difference and the mapping relationship.

12. The system for adjusting the memory of claim 11 , wherein the determination circuit comprises a first determination sub-circuit and a second determination sub-circuit;
wherein the first determination sub-circuit is configured to determine whether the temperature difference exceeds a first preset range;
the second determination sub-circuit is configured to determine whether the temperature difference exceeds a second preset range; and
wherein the second preset range is greater than the first preset range.

13. The system for adjusting of the memory of claim 8 , wherein the first acquisition circuit comprises:
a first acquisition sub-circuit, configured to acquire a first mapping relationship between the temperature of the transistor and the actual time at which the data is written into the memory;
a second acquisition sub-circuit, configured to acquire a second mapping relationship between the equivalent width-length ratio of the sense amplifier transistor in the sense amplifier and the actual time at which the data is written into the memory; and
a third acquisition sub-circuit, configured to, based on the first mapping re

Assignees

• Changxin Memory Tech Inc

Inventors

• Ning Shu-Liang
• He Jun
• Ying Zhan
• Liu Jie

Classifications

• G11C7/06 Primary

  Sense amplifiers; Associated circuits {, e.g. timing or triggering circuits} · CPC title

• G11C7/04 Primary

  with means for avoiding disturbances due to temperature effects · CPC title

• G11C7/1093 Primary

  Input synchronization · CPC title

• G11C7/1096

  Write circuits, e.g. I/O line write drivers · CPC title

• G11C7/12

  Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines · CPC title