Read disturb mitigation based on signal and noise characteristics of memory cells collected for read calibration

Patent metadata

Field	Value
Publication number	US-11984172-B2
Application number	US-202117536438-A
Country	US
Kind code	B2
Filing date	Nov 29, 2021
Priority date	Aug 7, 2020
Publication date	May 14, 2024
Grant date	May 14, 2024

Abstract

A memory device to perform a read disturb mitigation operation. For example, the memory device can measure signal and noise characteristics of a group of memory cells to determine an optimized read voltage of the group of memory cells and determine a margin of read disturb accumulated in the group of memory cells. Subsequently, the memory device can identify the group of memory cells for the read disturb mitigation operation based on the margin of read disturb and a predetermined threshold.

First claim

What is claimed is:

1. A device, comprising:
memory cells having voltage thresholds to represent data stored in the memory cells; and
a logic circuit configured to determine, based on characteristics of the memory cells, a voltage to read the memory cells and a margin of read disturb in the memory cells;
wherein the logic circuit is further configured to perform an operation to mitigate read disturb based on the margin of read disturb in the memory cells.

2. The device of claim 1 , further comprising:
an integrated circuit package configured to enclose the memory cells and the logic circuit.

3. The device of claim 2 , further comprising:
a calibration circuit configured to measure the signal and noise characteristics based on a plurality of counts determined at a plurality of test voltages respectively, wherein each respective count at a corresponding test voltage is, among the memory cells, a number of first memory cells that have a predetermined bit value when read at the corresponding test voltage.

4. The device of claim 2 , wherein the logic circuit is configured to calculate the voltage to read the memory cells from a distribution of count difference over a plurality of test voltages, wherein a count difference between two adjacent test voltages is a difference between a first count of a subset of the memory cells having a predetermined state when subjected to a first one of the adjacent test voltages and a second count of a subset of the memory cells having the predetermined state when subjected to a second one of the adjacent test voltages.

5. The device of claim 4 , wherein the logic circuit is configured to determine the margin of read disturb by applying the distribution of count difference as input to a predictive model.

6. The device of claim 5 , wherein the predictive model is trained using a machine learning technique.

7. The device of claim 5 , wherein the memory cells are configured to store multiple bits per memory cell and have a plurality of voltage levels for reading; and the voltage to read the memory cells is at a lowest level among the plurality of voltage levels.

8. The device of claim 5 , wherein the operation to mitigate read disturb includes retrieving the data from the memory cells and writing the data back to the device.

9. The device of claim 8 , wherein the logic circuit is further configured to:
identify, based on the margin of read disturb, a remaining number of read cycles endurable by the memory cells before a read failure.

10. The device of claim 4 , wherein the logic circuit is configured to determine the margin of read disturb based on an amount of shift in the voltage to read the memory cells.

11. A method, comprising:
programming voltage thresholds of memory cells of a device to represent data stored in the memory cells;
determining, by a logic circuit of the device, a voltage to read the memory cells, based on characteristics of the memory cells;
determining, by the logic circuit of the device, a margin of read disturb in the memory cells; and
determining, by the logic circuit of the device, whether to perform an operation to mitigate read disturb, based on the margin of read disturb in the memory cells.

12. The method of claim 11 , wherein the device has an integrated circuit package configured to enclose the memory cells and the logic circuit; and the method further comprises:
measuring, by a calibration circuit of the device, the signal and noise characteristics based on a plurality of counts determined at a plurality of test voltages respectively, wherein each respective count at a corresponding test voltage is, among the memory cells, a number of first memory cells that have a predetermined bit value when read at the corresponding test voltage.

13. The method of claim 11 , wherein the margin of read disturb is determined by applying the signal and noise characteristics as input to a predictive model trained using a machine learning technique.

14. The method of claim 11 , wherein the margin of read disturb is determined based on an amount of shift in the voltage to read the memory cells.

15. The method of claim 14 , wherein the operation to mitigate read disturb includes retrieving the data from the memory cells and writing the data back to the memory cells; and the method further comprises:
identifying, based on the margin of read disturb, a remaining number of read cycles endurable by the memory cells before a read failure.

16. An apparatus, comprising:
a processing device; and
a memory device enclosed within an integrated circuit package and connected to the processing device, the memory device having:
memory cells having voltage thresholds programmable to represent data stored in the memory cells;
a calibration circuit configured to measure signal and noise characteristics based on a plurality of counts determined at a plurality of test voltages respectively; and
a logic circuit configured to, in response to a read command from the processing device:
determine, based on the signal and noise characteristics of the memory cells, a voltage to read the memory cells and a margin of read disturb in the memory cells; and
determine, based on the margin of read disturb in the memory cells, whether to perform an operation to mitigate read disturb.

17. The apparatus of claim 16 , wherein the logic circuit is further configured to identify, based on the margin of read disturb, a remaining number of read cycles endurable by the memory cells before a read failure.

18. The apparatus of claim 17 , wherein the operation to mitigate read disturb includes retrieving the data from the memory cells and writing the data back to the memory cells.

Assignees

• Micron Technology Inc

Inventors

• Khayat Patrick Robert
• Fitzpatrick James
• Alhussien Abdelhakim S
• Parthasarathy Sivagnanam

Classifications

• G11C16/3431 Primary

  Circuits or methods to detect disturbed nonvolatile memory cells, e.g. which still read as programmed but with threshold less than the program verify threshold or read as erased but with threshold greater than the erase verify threshold, and to reverse the disturbance via a refreshing programming or erasing step · CPC title

• G06F18/214

  Generating training patterns; Bootstrap methods, e.g. bagging or boosting · CPC title

• G06N20/00

  Machine learning · CPC title

• G11C7/02

  with means for avoiding parasitic signals · CPC title

• G11C16/10

  Programming or data input circuits · CPC title