Nonvolatile memory device and storage device including the nonvolatile memory device

Patent metadata

Field	Value
Publication number	US-11984170-B2
Application number	US-202318160620-A
Country	US
Kind code	B2
Filing date	Jan 27, 2023
Priority date	Aug 7, 2020
Publication date	May 14, 2024
Grant date	May 14, 2024

Abstract

A nonvolatile memory device includes a first memory chip and a second memory chip connected to a controller through the same channel. The first memory chip generates a first signal from a first internal clock signal based on a clock signal received from the controller. The second memory chip generates a second signal from a second internal clock signal based on the clock signal, and performs a phase calibration operation on the second signal on the basis of a phase of the first signal by delaying the second internal clock signal based on a phase difference between the first and second signals.

First claim

What is claimed is:

1. A nonvolatile memory device comprising:
a buffer chip configured to generate a first clock signal and a second clock signal from a clock signal received from a controller;
a first memory chip configured to generate a first signal from a first internal clock signal, which is based on the first clock signal; and
a second memory chip configured to generate a second signal from a second internal clock signal, which is based on the second clock signal,
wherein the buffer chip is configured to perform a phase calibration operation on the second signal based on a phase of the first signal by delaying the second clock signal based on a phase difference between the first and second signals,
wherein at least one of the first memory chip or the second memory chip is a vertical NAND flash memory chip, and
wherein the vertical NAND flash memory chip includes,
word lines stacked on a substrate in a vertical direction, and
cell strings each including a plurality of memory cells, which are connected to the word lines, respectively.

2. The nonvolatile memory device of claim 1 , wherein
the first memory chip is configured to generate the first signal by performing a first duty correction operation on the first internal clock signal, and
the second memory chip is configured to generate the second signal by performing a second duty correction operation on the second internal clock signal.

3. The nonvolatile memory device of claim 2 , wherein the first and second duty correction operations are sequentially performed in response to a duty correction circuit (DCC) start command received from the controller.

4. The nonvolatile memory device of claim 2 , wherein the first and second duty correction operations are performed in parallel in response to a duty correction circuit (DCC) start command received from the controller.

5. The nonvolatile memory device of claim 1 , wherein
the first signal corresponds to a first data strobe signal generated by the first memory chip, and the second signal corresponds to a second data strobe signal generated by the second memory chip, and
the buffer chip is configured to delay the second clock signal based on a phase difference between the first and second data strobe signals.

6. The nonvolatile memory device of claim 1 , wherein the buffer chip comprises:
a phase detector configured to generate a phase detection signal according to the phase difference between the first and second signals, the first signal received through a first pin and the second signal received through a second pin;
a duty correction circuit (DCC) configured to generate a control signal by performing a duty correction operation on the phase detection signal; and
a delay circuit configured to delay the second clock signal according to the control signal.

7. The nonvolatile memory device of claim 1 , wherein the buffer chip comprises:
a delay circuit configured to delay the clock signal to generate the second clock signal;
a phase detector configured to generate a phase detection signal according to the phase difference between the first and second signals, the first signal received through a first pin and the second signal received through a second pin;
a control circuit configured to generate a control signal according to the phase detection signal; and
a delay cell configured to adjust a delay time with respect to the clock signal according to the control signal.

8. The nonvolatile memory device of claim 1 , wherein
the clock signal corresponds to a read enable signal,

the first clock signal corresponds to a first read enable signal, and
the second clock signal corresponds to a second read enable signal.

9. The nonvolatile memory device of claim 1 , wherein the buffer chip comprises a serializer/deserializer configured to convert serial data received from the controller into parallel data including first and second data, and transfer the first and second data to the first and second memory chips, respectively.

10. A nonvolatile memory device comprising:
a first memory device configured to generate a first signal from a first internal clock signal, which is based on a clock signal received by the first memory device from a controller; and
a second memory device configured to generate a second signal from a second internal clock signal, which is based on the clock signal, and perform a phase calibration operation on the second signal based on a phase difference between the first and second signals,
wherein the second memory device comprises,
a memory cell region including a first metal pad, and
a peripheral circuit region including a second metal pad and vertically connected to the memory cell region by the first metal pad and the second metal pad,

wherein the peripheral circuit region comprises,
a delay circuit configured to delay the clock signal to generate the second internal clock signal, and
a phase detector configured to detect the phase difference between the first and second signals, and generate a third signal having a duty ratio according to the detected phase difference or having a logic high level or a logic low level according to the detected phase difference, and

wherein the first metal pad and the second metal pad are connected in a bonding manner.

11. The nonvolatile memory device of claim 10 , wherein the peripheral circuit region further comprises a duty correction circuit (DCC) configured to perform a duty correction operation on the second internal clock signal and control the delay circuit based on the third signal.

12. The nonvolatile memory device of claim 10 , wherein the peripheral circuit region further comprises:
a control circuit configured to generate a control signal according to the third signal; and
a delay cell configured to adjust a delay time with respect to the second internal clock signal according to the control signal.

13. The nonvolatile memory device of claim 10 , wherein the first metal pad and the second metal pad comprise copper.

14. The nonvolatile memory device of claim 10 , wherein the memory cell region is on a first wafer, and the peripheral circuit region is on a second wafer.

15. The nonvolatile memory device of claim 10 , wherein
at least one of the first memory device or the second memory device is a vertical NAND flash memory device, and
the vertical NAND flash memory device includes,
word lines stacked on a substrate in a vertical direction, and
cell strings respectively including a plurality of memory cells respectively connected to the word lines.

16. The nonvolatile memory device of claim 10 , wherein each of the memory cell region and the peripheral circuit region comprises an external pad bonding area, a word line bonding area, and a bit line bonding area.

17. The nonvolatile memory device of claim 10 , wherein
the first memory device is configured to generate the first signal by performing a first duty correction operation on the first internal clock signal, and the second memory device is configured to generate the second signal by performing a second duty correction operation on the second internal clock signal, and
the first and second duty correction operations are sequentially performed in response to a duty correction circuit (DCC) start command received from the controller.

18. The nonvolatile memory device of claim 10 , wherein
the first memory device is configured to generate the first signal by performing a first duty correction operation on the first internal clock signal, and the second memory device is configu

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Tongsung
• Jo Youngmin
• Yoon Chiweon

Classifications

• H10W90/752

  between stacked chips · CPC title

• H10W90/00

  Package configurations · CPC title

• G11C16/32 Primary

  Timing circuits · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• H01L25/0657

  Electricity · mapped topic