Logic based read sample offset in a memory sub-system

Patent metadata

Field	Value
Publication number	US-11983065-B2
Application number	US-202117445395-A
Country	US
Kind code	B2
Filing date	Aug 18, 2021
Priority date	Jul 10, 2019
Publication date	May 14, 2024
Grant date	May 14, 2024

Abstract

The present disclosure is directed to logic based read sample offset operations in a memory sub-system. A processing device performs a first read, a second read, and a third read of data from a memory devices using a first center value corresponding to a first read level threshold, a negative offset value, and a positive offset value, respectively. The processing device performs a XOR operation on results from the first and second reads to obtain a first value and a XOR operation on results from the second and third reads to obtain a second value. The processing device performs a first count operation on the first value to determine a first difference bit count and a second count operation on the second value to determine a second difference bit count. The processing device can store or output the first difference bit count and the second difference bit count.

First claim

What is claimed is:

1. A memory system comprising:
one or more memory devices; and
a processing device coupled to the one or more memory devices, wherein the processing device is to:
perform a first exclusive-or (XOR) operation on results from a center read sample and results from a left read sample to obtain a first value;
perform a second XOR operation on the results from the center read sample and results of a right read sample to obtain a second value;
perform a first count operation on the first value to determine a first difference bit count;
perform a second count operation on the second value to determine a second difference bit count; and
determine, based on the first difference bit count and the second difference bit count, a difference bit count.

2. The memory system of claim 1 , wherein the center read sample corresponds to data read from the one or more memory devices using a center value corresponds to a first read level threshold, the left read sample corresponds to data read using a negative offset value that is lower than the center value, and right read sample corresponds to data read using a positive offset value that is higher than the center value.

3. The memory system of claim 1 , wherein the first count operation counts a number of ones in the first value resulting from the first XOR operation, wherein the number of ones in the first value indicates a number of bits that have changed between the center read sample and the left read sample, wherein the second count operation counts a number of ones in the second value resulting from the second XOR operation, wherein the number of ones in the second value indicates a number of bits that have changed between the center read sample and the right read sample.

4. The memory system of claim 1 , wherein the processing device comprises a logic circuit to perform the first XOR operation and the second XOR operation.

5. The memory system of claim 1 , wherein the processing device comprises:
a first logic circuit to perform the first XOR operation; and
a second logic circuit to perform the second XOR operation.

6. The memory system of claim 1 , wherein the processing device is a NAND controller and the one or more memory devices are NAND memory devices.

7. The memory system of claim 6 , wherein the NAND controller performs a continuous read level calibration (cRLC) operation on the one or more memory device using the first difference bit count and the second difference count without sending the results from the center read sample, the left read sample, and the right read sample to an Error Correction Code (ECC) decoder.

8. The memory system of claim 7 , wherein the first difference bit count exceeds a correction capability of the ECC decoder.

9. The memory system of claim 2 , wherein the processing device is further to:
perform a third XOR operation on results from a second center read sample and results from a second left read sample to obtain a third value;
perform a fourth XOR operation on the results from the second center read sample and results from a second right read sample to obtain a fourth value;
perform a third count operation on the third value to determine a third difference bit count;
perform a fourth count operation on the fourth value to determine a fourth difference bit count; and
determine, based on the third difference bit count and the fourth difference bit count, a second difference bit count.

10. The memory system of claim 9 , wherein the second center read sample corresponds to a second data read from the one or more memory devices using a second center value corresponding to a second read level threshold, the second left read sample corresponds to the second data read using a second negative offset that is lower than the second center value, and the second right read sample corresponds to the second data read using a second positive offset that is higher than the second center value.

11. The memory system of claim 9 , wherein the center read sample and the second center read sample are performed concurrently, wherein the left read sample and the second left read sample are performed concurrently, and wherein the right read sample and the second right read sample are performed concurrently.

12. The memory system of claim 10 , wherein the first read level threshold and the second read level threshold correspond to a same page type.

13. The memory system of claim 1 , wherein the processing device resides in the one or more memory devices, and wherein the processing device is further to send the first difference bit count and the second difference bit count to a controller of the memory system.

14. The memory system of claim 2 , wherein the processing device uses a read sample offset (RSO) mask register to mask one or more read level thresholds of a page type and disable the first read level threshold, wherein the center read sample, the left read sample, and the right read sample are part of a RSO page read from a page that provides three-strobe results with bit error rate (BER) differences limited to the first read level threshold.

15. The memory system of claim 2 , wherein the processing device uses a read sample offset (RSO) mask register to mask one or more read level thresholds of a page type and disable the first read level threshold and a second read level threshold, wherein the center read sample, the left read sample, and the right read sample are part of a RSO page read from a page that provides three-strobe results bit error rate (BER) differences limited to the first read level threshold and the second read level threshold.

16. A system comprising:
a host system;
an interconnect; and
a memory sub-system coupled to the host system over the interconnect, wherein the memory sub-system comprises one or more memory devices and a processing device, wherein the processing device is to:
perform a first XOR operation on a right sample data from data stored in the one or more memory devices and a center sample data from data stored in the one or more memory devices;
perform a second XOR operation on a left sample data from data stored in the one or more memory devices and the center sample data;
count a first number of ones resulting from the first XOR operation, wherein the first number is a right difference bit count (DBC),
count a second number of ones resulting from the second XOR operation, wherein the second number is a left DBC;
determine, based on the right DBC and the left DBC, a difference bit count; and
perform a subsequent operation using the difference bit count.

17. The system of claim 16 , wherein the memory sub-system further comprises a controller coupled to the one or more memory devices, wherein the processing device resides in the one or more memory devices, and wherein the subsequent operation comprises sending the right DBC and the left DBC to the controller.

18. The system of claim 16 , wherein the memory sub-system further comprises a controller coupled to the one or more memory devices, wherein the processing device resides in the one or more memory devices, wherein the controller comprises an Error Correction Code (ECC) decoder, and wherein the subsequent operation is a continuous read level calibration (cRLC) operation using the right DBC and the left DBC without sending the right sample data, center sample data, and left sample data to the ECC decoder.

19. The system of claim 16 , wherein the subsequent operation is at least one of:
a continuous read level calibration (cRLC) operation;
a read level

Assignees

• Micron Technology Inc

Inventors

• Liikanen Bruce A
• Sheperek Michael

Classifications

• G06F11/1048 Primary

  using arrangements adapted for a specific error detection or correction feature · CPC title

• G06F3/0619

  in relation to data integrity, e.g. data losses, bit errors · CPC title

• G06F3/0658

  Controller construction arrangements · CPC title

• G06F3/0683

  Plurality of storage devices · CPC title

• G06F3/0688 Primary

  Non-volatile semiconductor memory arrays · CPC title