Memory device with dynamic programming calibration

Patent metadata

Field	Value
Publication number	US-10402272-B2
Application number	US-201715605853-A
Country	US
Kind code	B2
Filing date	May 25, 2017
Priority date	May 25, 2017
Publication date	Sep 3, 2019
Grant date	Sep 3, 2019

Abstract

A memory system includes a memory array including a plurality of memory cells; and a controller coupled to the memory array, the controller configured to: determine background records associated with a programming step, wherein the background records are for representing previous data operations, calculate a trigger measure based on the background records, wherein the trigger measure is for estimating implementation of an error recovery mechanism, and generate an adjusted step based on the trigger measure.

First claim

We claim:

1. A memory device, comprising:
a memory array including a plurality of memory cells; and
a controller coupled to the memory array, the controller configured to:
determine background records associated with a programming step, wherein:
the programming step represents a charge increment for a write operation, wherein the write operation includes iteratively increasing stored charge at a memory cell by the charge increment, and
the background records are for representing previous data operations,

calculate a trigger measure based on the background records, wherein the trigger measure is for estimating implementation of an error recovery mechanism, and
adjust the programming step based on the trigger measure.

2. The memory device of claim 1 wherein the controller is further configured to determine the background records based on storing an error measure occurring during operation of the memory array.

3. The memory device of claim 1 wherein the controller is further configured to:
calculate the trigger measure including a trigger rate for estimating a frequency of implementing the error recovery mechanism; and
adjust the programming step based on the trigger rate.

4. The memory device of claim 1 wherein the controller is further configured to:
calculate the trigger measure including a trigger margin for representing a relationship between a system trigger condition and an error count; and
adjust the programming step based on the trigger margin.

5. The memory device of claim 1 wherein the controller is further configured to adjust the programming step based on implementing a processing-level calibration mechanism to iteratively calibrate a processing level during operation of the memory device.

6. The memory device of claim 1 wherein the controller is further configured to adjust the programming step based on implementing a target calibration mechanism to calibrate a target profile during operation of the memory device.

7. The memory device of claim 6 wherein the controller is further configured to implement a step calibration mechanism to adjust the programming step less frequently than implementing the target calibration mechanism.

8. The memory device of claim 1 wherein the controller is further configured to:
determine a hysteresis parameter for controlling repetitive patterns of adjusting the programming step; and
adjust the programming step based on the hysteresis parameter.

9. The memory device of claim 1 wherein the controller is further configured to adjust the programming step for balancing a programming time and an error measure associated with writing the data in the memory array.

10. The memory device of claim 1 wherein the controller is further configured to adjust the programming step for maintaining the trigger measure at or within a range of a target value.

11. The memory device of claim 1 wherein the controller is further configured to adjust the programming step for increasing or decreasing a programming time associated with the programming step.

12. The memory device of claim 1 wherein the controller is further configured to adjust the programming step for or during a drive fill.

13. The memory device of claim 1 wherein the controller is further configured to calculate the trigger measure using an estimation mechanism for estimating a projection of an error count.

14. The memory device of claim 1 wherein the controller is further configured to calculate the trigger measure directly from an error count.

15. The memory device of claim 1 wherein the controller is further configured to:
determine the background records based on tracking an error count associated with code-word and the programming step;
determine a trigger control profile for representing a threshold in calibrating the programming step; and
adjust the programming step based on comparing the trigger control profile and the trigger measure, wherein the adjustment is for providing a calibrated value of the programming step.

16. The memory device of claim 15 wherein the controller is further configured to:
generate a cumulative distribution function based on the background records for normalizing the background records; and
calculate the trigger measure based on the cumulative distribution function or a processing result thereof.

17. The memory device of claim 16 wherein the controller is further configured to generate the cumulative distribution function for each iteration or implementation of a step calibration mechanism to calibrate the programming step, or based on iteratively updating the cumulative distribution function.

18. A method of operating a memory device including a controller and memory cells, wherein the method comprising:
determining background records associated with a programming step, wherein:
the programming step represents a charge increment for a write operation, wherein the write operation includes iteratively increasing stored charge at a memory cell by the charge increment, and
the background records are for representing previous data operations;

calculating a trigger measure based on the background records, wherein the trigger measure is for estimating implementation of an error recovery mechanism; and
adjusting using the controller, the programming step based on the trigger measure.

19. The method of claim 18 , wherein determining the background records includes storing an error measure over operation of the memory array.

20. The method of claim 18 , wherein:
calculating the trigger measure includes calculating a trigger rate for estimating a frequency of implementing the error recovery mechanism; and
adjusting the programming step includes adjusting the programming step based on the trigger rate.

21. The method of claim 18 , wherein:
calculating the trigger measure includes calculating a trigger margin for representing a relationship between a system trigger condition and an error count; and
adjusting the programming step includes adjusting the programming step based on the trigger margin.

22. The method of claim 18 , wherein adjusting the programming step includes adjusting the programming step for maintaining the trigger measure at or within a range of a target value.

23. The method of claim 18 , wherein adjusting the programming step includes adjusting the programming step for or during a drive fill.

24. The method of claim 18 , further comprising:
generating a cumulative distribution function based on the background records for normalizing the background records; and

wherein:
calculating the trigger measure includes calculating the trigger measure based on the cumulative distribution function or a processing result thereof.

25. The method of claim 24 , wherein generating the cumulative distribution function includes iteratively updating the cumulative distribution function for each iteration or calibration of the programming step.

Assignees

• Micron Technology Inc

Inventors

• Liikanen Bruce A
• Koudele Larry J

Classifications

• G11C16/3459 Primary

  Circuits or methods to verify correct programming of nonvolatile memory cells · CPC title

• G11C11/5628

  Programming or writing circuits; Data input circuits · CPC title

• G06F11/142 Primary

  Reconfiguring to eliminate the error (group management mechanisms in a peer-to-peer network H04L67/1044) · CPC title

• G11C16/10

  Programming or data input circuits · CPC title

• G06F11/0757

  by exceeding a time limit, i.e. time-out, e.g. watchdogs · CPC title