Pixel circuit having increased capacitance and display device including the same

Patent metadata

Field	Value
Publication number	US-11980060-B2
Application number	US-202117494892-A
Country	US
Kind code	B2
Filing date	Oct 6, 2021
Priority date	Dec 1, 2020
Publication date	May 7, 2024
Grant date	May 7, 2024

Abstract

A display device includes a first lower electrode disposed on a base substrate, a first upper electrode disposed on the first lower electrode, overlapping the first lower electrode in a plan view, including a silicon semiconductor, and constituting a first capacitor together with the first lower electrode, a second lower electrode disposed on the first upper electrode, and a second upper electrode disposed on the second lower electrode, overlapping the second lower electrode in a plan view, including an oxide semiconductor, and constituting a second capacitor together with the second lower electrode.

First claim

What is claimed is:

1. A display device comprising:
a first lower electrode disposed on a base substrate;
a first upper electrode disposed on the first lower electrode, overlapping the first lower electrode in a plan view, including a silicon semiconductor, and constituting a first capacitor together with the first lower electrode;
a second lower electrode disposed on the first upper electrode; and
a second upper electrode disposed on the second lower electrode, overlapping the second lower electrode in a plan view, including an oxide semiconductor, and constituting a second capacitor together with the second lower electrode,
wherein the first capacitor and the second capacitor are connected in parallel.

2. The display device of claim 1 , wherein the first lower electrode and the second upper electrode are electrically connected to each other.

3. The display device of claim 1 , wherein a high power voltage is provided to the first lower electrode and the second upper electrode.

4. The display device of claim 1 , wherein the first upper electrode and the second lower electrode are electrically connected to each other.

5. The display device of claim 1 , wherein the first lower electrode and the second lower electrode comprise a same material.

6. The display device of claim 1 , further comprising:
a first active pattern disposed on a same layer as the first upper electrode and overlapping the second lower electrode in a plan view.

7. The display device of claim 6 , further comprising:
a first lower gate electrode disposed on a same layer as the first lower electrode and overlapping the second lower electrode in a plan view.

8. The display device of claim 7 , wherein a gate signal is provided to the first lower gate electrode and the second lower electrode.

9. The display device of claim 5 , wherein the first lower electrode and the second lower electrode comprise molybdenum.

10. The display device of claim 1 , further comprising:
a second active pattern disposed on a same layer as the second upper electrode; and
an upper gate electrode disposed on the second active pattern and overlapping the second active pattern in a plan view.

11. The display device of claim 10 , wherein the first lower electrode and the first upper electrode overlap the upper gate electrode in a plan view.

12. The display device of claim 10 , wherein the first lower electrode and the first upper electrode do not overlap the upper gate electrode in a plan view.

13. The display device of claim 12 , further comprising:
a second lower gate electrode disposed on a same layer as the second lower electrode and overlapping the upper gate electrode in a plan view.

14. The display device of claim 13 , wherein a gate signal is provided to the upper gate electrode and the second lower gate electrode.

15. A display device comprising:
a first lower electrode disposed on a base substrate;
an upper electrode disposed on the first lower electrode, overlapping the first lower electrode in a plan view, including a silicon semiconductor, and constituting a capacitor together with the first lower electrode;
a first active pattern disposed on a same layer as the upper electrode;
a second lower electrode disposed on the first active pattern and overlapping the first active pattern in a plan view;
a second active pattern disposed on the second lower electrode and including an oxide semiconductor; and
an upper gate electrode disposed on the second active pattern and overlapping the second active pattern in a plan view.

16. The display device of claim 15 , further comprising:
a first lower gate electrode disposed on a same layer as the first lower electrode and overlapping the second lower electrode in a plan view.

17. The display device of claim 16 , wherein a gate signal is provided to the second lower electrode and the first lower gate electrode.

18. The display device of claim 15 , wherein the first lower electrode and the upper electrode overlap the upper gate electrode in a plan view.

19. The display device of claim 15 , wherein the first lower electrode and the upper electrode do not overlap the upper gate electrode in a plan view.

20. The display device of claim 19 , further comprising:
a second lower gate electrode disposed on a same layer as the second lower electrode and overlapping the upper gate electrode in a plan view.

21. The display device of claim 20 , wherein a gate signal is provided to the upper gate electrode and the second lower gate electrode.

22. A display device comprising:
a first active pattern disposed on a base substrate and including a silicon semiconductor;
a lower electrode disposed on the first active pattern;
an upper electrode disposed on the lower electrode, overlapping the lower electrode in a plan view, including an oxide semiconductor, and constituting a capacitor together with the lower electrode;
a second active pattern disposed on a same layer as the upper electrode;
an upper gate electrode disposed on the second active pattern; and
a first lower electrode disposed under the first active pattern and overlapping the lower electrode in a plan view.

23. The display device of claim 22 , wherein a gate signal is provided to the lower electrode and the first lower gate electrode.

24. The display device of claim 22 , further comprising:
a second lower gate electrode disposed on a same layer as the lower electrode and overlapping the upper gate electrode in a plan view.

Assignees

• Samsung Display Co Ltd

Inventors

• Kim Myeongho
• Kim Yeonhong
• Kim Jaybum
• Son Kyoung Seok
• Lee Sunhee
• Lee Seungjun
• Lee Seunghun
• Lim Jun Hyung

Classifications

• H10K71/00

  Manufacture or treatment specially adapted for the organic devices covered by this subclass · CPC title

• H10D86/441

  Interconnections, e.g. scanning lines · CPC title

• H10D86/481

  integrated with passive devices, e.g. auxiliary capacitors · CPC title

• H10D86/60

  wherein the TFTs are in active matrices · CPC title

• H10K59/1216 Primary

  the pixel elements being capacitors · CPC title