Display substrate including additional insulating layer between transistor gate and active layer for preventing dark spots, preparation method thereof, and display apparatus

Patent metadata

Field	Value
Publication number	US-11980058-B2
Application number	US-202117486790-A
Country	US
Kind code	B2
Filing date	Sep 27, 2021
Priority date	Nov 13, 2020
Publication date	May 7, 2024
Grant date	May 7, 2024

Abstract

A display substrate, a preparation method thereof, and a display apparatus are provide. The display substrate includes: a base substrate, an active layer disposed on the base substrate, a first gate insulating layer disposed on the active layer, a first conductive layer disposed on the first gate insulating layer, and a second conductive layer disposed on the first conductive layer and electrically connected with the first conductive layer; an orthographic projection of the first conductive layer on the base substrate does not overlap with an orthographic projection of the active layer on the base substrate; the second conductive layer includes gates; orthographic projections of the gates on the base substrate and the orthographic projection of the active layer on the base substrate have an overlap area; and the display substrate further includes: at least one insulating layer located between the first conductive layer and the gates.

First claim

What is claimed is:

1. A display substrate, comprising:
a base substrate;
an active layer disposed on the base substrate;
a first gate insulating layer disposed on the active layer;
a first conductive layer disposed on the first gate insulating layer; and
a second conductive layer disposed on the first conductive layer and electrically connected with the first conductive layer, wherein
an orthographic projection, on the base substrate, of the first conductive layer does not overlap with an orthographic projection, on the base substrate, of the active layer;
the second conductive layer comprises gates, and orthographic projections, on the base substrate, of the gates and the orthographic projection, on the base substrate, of the active layer have an overlap area; and

the display substrate further comprises:
at least one insulating layer disposed between the first conductive layer and the gates.

2. The display substrate according to claim 1 , wherein the at least one insulating layer comprises a first insulating layer; wherein
the first conductive layer comprises a first connection lead part and a second connection lead part respectively disposed on two sides of the active layer;
the first insulating layer is provided with a first via hole exposing the first connection lead part and a second via hole exposing the second connection lead part; and
at least one of the gates is electrically connected with the first connection lead part through the first via hole, and is electrically connected with the second connection lead part through the second via hole.

3. The display substrate according to claim 2 , further comprising:
a third conductive layer disposed between the first insulating layer and the gates, wherein
the at least one insulating layer further comprises a second insulating layer disposed between the third conductive layer and the gates.

4. The display substrate according to claim 2 , wherein the second conductive layer further comprises sources and drains.

5. The display substrate according to claim 2 , further comprising:
a third insulating layer disposed on the second conductive layer; and
a source and drain electrode layer disposed on the third insulating layer, wherein the source and drain electrode layer comprises sources and drains.

6. The display substrate according to claim 1 , further comprising:
a light shielding layer disposed between the base substrate and the active layer.

7. The display substrate according to claim 1 , further comprising:
a protective layer disposed on the second conductive layer.

8. A preparation method of the display substrate according to claim 1 , comprising:
forming the active layer on the base substrate;
forming the first gate insulating layer on the active layer;
forming a pattern of the first conductive layer on the first gate insulating layer, wherein the orthographic projection, on the base substrate, of the first conductive layer does not overlaps with the orthographic projection, on the base substrate, of the active layer;
forming the at least one insulating layer on the first conductive layer; and
forming the second conductive layer electrically connected with the first conductive layer on the at least one insulating layer, wherein the second conductive layer comprises the gates, and the orthographic projections, on the base substrate, of the gates and the orthographic projection, on the base substrate, of the active layer have the overlap area.

9. The method according to claim 8 , wherein the forming the at least one insulating layer on the first conductive layer, comprises:
forming a first insulating layer on the first conductive layer, and
forming a via hole penetrating through the first insulating layer and exposing the first conductive layer; and
the forming the second conductive layer electrically connected with the first conductive layer on the at least one insulating layer comprises:
depositing a conductive material on the first insulating layer to form the second conductive layer, and forming a pattern of the gates by adopting a patterning process, wherein at least one of the gates is electrically connected with the first conductive layer through the via hole.

10. The method according to claim 8 , wherein the forming the pattern of the first conductive layer, comprises:
depositing a conductive material on the first gate insulating layer to form the first conductive layer;
coating photoresist on the first conductive layer;
performing patterning treatment on the photoresist by adopting a halftone mask process, removing all the photoresist in a first region, thinning the photoresist in a second region, and reserving the photoresist in a third region, wherein in the second region, the orthographic projection, on the base substrate, of the active layer and the orthographic projection, on the base substrate, of the first conductive layer have an overlap area;
removing the first conductive layer in the first region by adopting a wet etching process;
removing the photoresist in the second region, and thinning the photoresist in the third region;
removing the first conductive layer in the second region by adopting the wet etching process; and
stripping off the photoresist in the third region.

11. The method according to claim 8 , wherein while forming the pattern of the gate by adopting the patterning process, the method further comprises:
forming patterns of sources and drains.

12. A display apparatus, comprising a display substrate, wherein the display substrate comprises:
a base substrate;
an active layer disposed on the base substrate;
a first gate insulating layer disposed on the active layer;
a first conductive layer disposed on the first gate insulating layer; and
a second conductive layer disposed on the first conductive layer and electrically connected with the first conductive layer;
an orthographic projection, on the base substrate, of the first conductive layer does not overlap with an orthographic projection, on the base substrate, of the active layer;
the second conductive layer comprises: gates, and orthographic projections, on the base substrate, of the gates and the orthographic projection, on the base substrate, of the active layer have an overlap area; and
the display substrate further comprises:
at least one insulating layer located between the first conductive layer and the gates.

13. The display apparatus according to claim 12 , wherein
the at least one insulating layer comprises a first insulating layer disposed;
the first conductive layer comprises a first connection lead part and a second connection lead part respectively disposed on two sides of the active layer;
the first insulating layer is provided with a first via hole exposing the first connection lead part and a second via hole exposing the second connection lead part; and
at least one of the gates is electrically connected with the first connection lead part through the first via hole, and is electrically connected with the second connection lead part through the second via hole.

14. The display apparatus according to claim 13 , wherein
the display substrate further comprises a third conductive layer disposed between the first insulating layer and the gates; and
the at least one insulating layer further comprises a second insulating layer disposed between the third conductive layer and the gates.

15. The display apparatus according to claim 13 , wherein the display substrate comprises:
a third insulating layer disposed on the second conductive layer; and
a source and drain electrode layer disposed

Assignees

• Hefei Xinsheng Optoelectronics Technology Co Ltd
• Boe Technology Group Co Ltd

Inventors

• Wang Haitao
• Wang Qinghe
• Wang Jun
• Su Tongshang
• Cheng Jun

Classifications

• H10K71/00

  Manufacture or treatment specially adapted for the organic devices covered by this subclass · CPC title

• H10K59/131

  Interconnections, e.g. wiring lines or terminals · CPC title

• H10K59/1213 Primary

  the pixel elements being TFTs · CPC title

• H10K59/1201 Primary

  Manufacture or treatment · CPC title

• H10D30/6755

  Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate · CPC title