Pixel structure and method of fabricating the same

Patent metadata

Field	Value
Publication number	US-9437618-B2
Application number	US-201414321825-A
Country	US
Kind code	B2
Filing date	Jul 2, 2014
Priority date	Jan 29, 2014
Publication date	Sep 6, 2016
Grant date	Sep 6, 2016

Abstract

A pixel structure includes a thin film transistor device. The thin film transistor device includes a first connection electrode, a second connection electrode, an oxide semiconductor channel layer, a gate insulation layer, a gate electrode, a dielectric layer, a source electrode and a drain electrode. The oxide semiconductor channel layer at least partially covers a top surface of the first connection electrode and a top surface of the second connection electrode. The gate electrode is disposed on the gate insulation layer. The dielectric layer is disposed on the gate electrode and the gate insulation layer. The gate insulation layer and the dielectric layer have a first contact hole at least partially exposing the top surface of the first connection electrode and a second contact hole at least partially exposing the top surface of the second connection electrode. The source electrode is electrically connected to the first connection electrode via the first contact hole, and the drain electrode is electrically connected to the second connection electrode via the second contact hole.

First claim

What is claimed is:

1. A pixel structure, comprising:
a substrate;
a thin film transistor device, disposed on the substrate, the thin film transistor device comprising:
a first connection electrode and a second connection electrode, disposed on the substrate, wherein the first connection electrode and the second connection electrode comprise conductive materials respectively;
an oxide semiconductor channel layer, disposed on the substrate, wherein the oxide semiconductor channel layer has two opposite sides partially overlapping a top surface of the first connection electrode and a top surface of the second connection electrode respectively, and the first connection electrode and the second connection electrode are disposed between the oxide semiconductor channel layer and the substrate;
a gate insulation layer, disposed on the substrate and covering the oxide semiconductor channel layer, the first connection electrode and the second connection electrode;
a gate electrode, disposed on the gate insulation layer;
a dielectric layer, disposed on the gate electrode and the gate insulation layer, wherein the gate insulation layer and the dielectric layer have a first contact hole at least partially exposing the top surface of the first connection electrode, and a second contact hole at least partially exposing the top surface of the second connection electrode; and
a source electrode and a drain electrode, disposed on the dielectric layer, wherein the source electrode is electrically connected to the first connection electrode through the first contact hole so as to form an entire source electrode by the source electrode and the first connection electrode, and the drain electrode is electrically connected to the second connection electrode through the second contact hole so as to form an entire drain electrode by the drain electrode and the second connection electrode;

a first passivation layer, disposed on the dielectric layer, wherein the first passivation layer has a third contact hole at least partially exposing the drain electrode; and
a first pixel electrode, disposed on the first passivation layer, wherein the first pixel electrode is electrically connected to the drain electrode of the thin film transistor device through the third contact hole.

2. The pixel structure of claim 1 , wherein the first connection electrode and the second connection electrode comprise metal electrodes.

3. The pixel structure of claim 1 , wherein the first connection electrode and the second connection electrode comprise metal oxide conductive electrodes.

4. The pixel structure of claim 1 , wherein the thin film transistor device further comprises a protection pattern disposed between the oxide semiconductor channel layer and the gate insulation layer, and the protection pattern comprises an insulating material.

5. The pixel structure of claim 1 , further comprising:
a display medium layer, disposed on the first pixel electrode; and
a second pixel electrode, disposed on the display medium layer.

6. The pixel structure of claim 5 , wherein the display medium layer is an organic electroluminescent layer.

7. The pixel structure of claim 5 , further comprising a second passivation layer disposed on the first passivation layer, wherein the second passivation layer has an opening at least partially exposing the first pixel electrode, and the display medium layer is disposed in the opening of the second passivation layer.

8. The pixel structure of claim 1 , further comprising a storage capacitor device, wherein the storage capacitor device comprises:
a storage capacitor bottom electrode, disposed on the substrate; and
a storage capacitor top electrode, disposed on the gate insulation layer.

9. The pixel structure of claim 8 , wherein the storage capacitor bottom electrode, the first connection electrode and the second connection electrode are made of a first patterned conductive layer, and the storage capacitor top electrode and the gate electrode are made of a second patterned conductive layer.

10. The pixel structure of claim 1 , further comprising a first protection film disposed between the dielectric layer and the first passivation layer.

11. The pixel structure of claim 1 , further comprising a second protection film disposed between the substrate and the first connection electrode, and between the substrate and the second connection electrode.

12. A method of fabricating pixel structure, comprising:
providing a substrate;
forming a first patterned conductive layer on the substrate, wherein the first patterned conductive layer comprises a first connection electrode and a second connection electrode, and the first connection electrode and the second connection electrode comprise conductive materials respectively;
forming an oxide semiconductor channel layer on the substrate, wherein the oxide semiconductor channel layer has two opposite sides partially overlapping a top surface of the first connection electrode and a top surface of the second connection electrode respectively, and the first connection electrode and the second connection electrode are disposed between the oxide semiconductor channel layer and the substrate;
forming a gate insulation layer on the substrate, wherein the gate insulation layer covers the oxide semiconductor channel layer, the first connection electrode and the second connection electrode;
forming a second patterned conductive layer on the gate insulation layer, wherein the second patterned conductive layer comprises a gate electrode;
forming a dielectric layer on the gate electrode and the gate insulation layer;
forming a first contact hole in the gate insulation layer and the dielectric layer to at least partially expose the top surface of the first connection electrode, and a second contact hole in the gate insulation layer and the dielectric layer to at least partially expose the top surface of the second connection electrode;
forming a third patterned conductive layer on the dielectric layer, wherein the third patterned conductive layer comprises a source electrode and a drain electrode, the source electrode is electrically connected to the first connection electrode through the first contact hole so as to form a complete source electrode, and the drain electrode is electrically connected to the second connection electrode through the second contact hole so as to form a complete drain electrode;
forming a first passivation layer on the dielectric layer, wherein the first passivation layer has a third contact hole at least partially exposing the drain electrode; and
forming a first pixel electrode on the first passivation layer, wherein the first pixel electrode is electrically connected to the drain electrode of the thin film transistor device through the third contact hole.

13. The method of fabricating pixel structure of claim 12 , further comprising:
forming a second passivation layer on the first passivation layer, wherein the second passivation layer has an opening at least partially exposing the first pixel electrode;
forming a display medium layer in the opening of the second passivation layer; and
forming a second pixel electrode on the display medium layer.

14. The method of fabricating pixel structure of claim 13 , wherein the display medium layer is an organic electroluminescent layer.

15. The method of fabricating pixel structure of claim 12 , wherein the first patterned conductive layer further comprises a storage capacitor bottom electrode, and the second patterned conductive layer further comprises a storage capacitor top electrode.

16. The met

Assignees

• Au Optronics Corp

Inventors

• Chou Cheng-Wei

Classifications

• H10D99/00

  Subject matter not provided for in other groups of this subclass · CPC title

• H10D86/481

  integrated with passive devices, e.g. auxiliary capacitors · CPC title

• H10D86/423 Primary

  comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO · CPC title

• H10D86/60 Primary

  wherein the TFTs are in active matrices · CPC title

• H10D30/6727

  having source or drain regions connected to bulk conducting substrates · CPC title