Single-ended direct interface dual DAC feedback photo-diode sensor

Patent metadata

Field	Value
Publication number	US-11979173-B2
Application number	US-202318103614-A
Country	US
Kind code	B2
Filing date	Jan 31, 2023
Priority date	Nov 8, 2019
Publication date	May 7, 2024
Grant date	May 7, 2024

Abstract

An analog to digital converter (ADC) that is configured to service a photo-diode includes a capacitor and a self-referenced latched comparator. The capacitor produces a photo-diode voltage based on charging by a photo-diode current associated with the photo-diode and a digital to analog converter (DAC) source current and/or a DAC sink current. The self-referenced latched comparator generates a first digital signal that is based on a difference between the photo-diode voltage and a threshold voltage associated with the self-referenced latched comparator. Also, one or more processing modules executes operational instructions to process the first digital signal to generate a second digital signal and/or a third digital signal. An N-bit DAC generates the DAC source current based on the second digital signal, and an M-bit DAC generates the DAC sink current based on the third digital signal. The DAC source current and/or the DAC sink current tracks the photo-diode current.

First claim

What is claimed is:

1. An analog to digital converter (ADC) comprising:
a capacitor that is operably coupled to a photo-diode and configured to produce a photo-diode voltage based on charging by at least one of a photo-diode current associated with the photo-diode and at least one of a digital to analog converter (DAC) source current or a DAC sink current, wherein the ADC is coupled to the photo-diode via a single line;
a self-referenced latched comparator operably coupled to the photo-diode and the capacitor and configured to generate a first digital signal that is based on the photo-diode voltage, wherein the DAC sink current configured to maintain a voltage at an input of the self-referenced latched comparator at a threshold voltage associated with the self-referenced latched comparator based on no photo-diode current being provided from the photo-diode;
memory that stores operational instructions; and
one or more processing modules that is operably coupled to the self-referenced latched comparator and the memory and configured to execute the operational instructions to process the first digital signal to generate at least one of a second digital signal or a third digital signal that control the at least one of the DAC source current or a DAC sink current.

2. The ADC of claim 1 further comprising:
an N-bit DAC that is operably coupled to the one or more processing modules and configured to generate the DAC source current based on the second digital signal, wherein N is a first positive integer; and
an M-bit DAC that is operably coupled to the one or more processing modules and configured to generate the DAC sink current based on the third digital signal, wherein M is a second positive integer, wherein the at least one of the DAC source current or the DAC sink current tracks the photo-diode current.

3. The ADC of claim 2 further comprising:
a first one or more processing modules of the one or more processing modules that is operably coupled to the self-referenced latched comparator, the memory, and the N-bit DAC and configured to execute first operational instructions to process the first digital signal to generate the second digital signal and to provide the second digital signal to the N-bit DAC; and
a second one or more processing modules of the one or more processing modules that is operably coupled to the self-referenced latched comparator, the memory, and the M-bit DAC and configured to execute second operational instructions to process the first digital signal to generate the third digital signal and to provide the second digital signal to the M-bit DAC.

4. The ADC of claim 2 further comprising:
a first one or more processing modules of the one or more processing modules that is operably coupled to the self-referenced latched comparator, the memory, and the N-bit DAC and configured to execute first operational instructions to process the first digital signal to generate a fourth digital signal; and
a second one or more processing modules of the one or more processing modules that is operably coupled to the self-referenced latched comparator, the memory, and the M-bit DAC and configured to execute second operational instructions to process the first digital signal to generate a fifth digital signal.

5. The ADC of claim 4 further comprising:
a first decimation filter operably coupled to the first one or more processing modules and configured to process the fourth digital signal to generate a first digital output signal having a lower sampling rate and a higher resolution than the fourth digital signal; and
a second decimation filter operably coupled to the second one or more processing modules and configured to process the fifth digital signal to generate a second digital output signal having a lower sampling rate and a higher resolution than the fifth digital signal.

6. The ADC of claim 2 , wherein:
the N-bit DAC is a higher power consuming component than the M-bit DAC;
N is greater than M; and
the DAC source current is larger than the DAC sink current.

7. The ADC of claim 2 , wherein N is equal to M.

8. The ADC of claim 2 further comprising
the N-bit DAC is further configured to generate and provide the DAC source current based on the photo-diode voltage comparing favorably to a predetermined voltage, wherein N is a first positive integer; and
the M-bit DAC is further configured to generate and provide the DAC sink current based on the photo-diode voltage comparing unfavorably to the predetermined voltage, wherein the at least one of the DAC source current or the DAC sink current tracks the photo-diode current.

9. The ADC of claim 8 , wherein:
the photo-diode voltage comparing favorably to the predetermined voltage based on the photo-diode voltage being greater than the predetermined voltage; and
the photo-diode voltage comparing unfavorably to the predetermined voltage based on the photo-diode voltage being less than the predetermined voltage.

10. The ADC of claim 1 , wherein the self-referenced latched comparator further comprising:
a first inverter operably coupled to the photo-diode and the capacitor;
a second inverter operably coupled to the first inverter; and
a digital circuit operably coupled to the second inverter and configured to output the first digital signal.

11. The ADC of claim 1 , wherein the self-referenced latched comparator further comprising:
a first inverter operably coupled to the photo-diode and the capacitor;
a second inverter operably coupled to the first inverter;
a third inverter including an input operably coupled to an output of the second inverter and an output operably coupled to a node coupling an output of the first inverter to an input of the second inverter via a switch to facilitate operation of the self-referenced latched comparator in accordance with a sampling mode and a latched mode; and
a digital circuit operably coupled to the second inverter and configured to output the first digital signal.

12. The ADC of claim 1 further comprising:
a decimation filter operably coupled to the one or more processing modules and configured to process the first digital signal to generate a digital output signal having a lower sampling rate and a higher resolution than the first digital signal.

13. The ADC of claim 1 further comprising:
a decimation filter operably coupled to the one or more processing modules and configured to process the second digital signal to generate a digital output signal having a lower sampling rate and a higher resolution than the second digital signal.

14. An analog to digital converter (ADC) comprising:
a capacitor that is operably coupled to a photo-diode and configured to produce a photo-diode voltage based on charging by at least one of a photo-diode current associated with the photo-diode and at least one of a digital to analog converter (DAC) source current or a DAC sink current, wherein the ADC is coupled to the photo-diode via a single line;
a self-referenced latched comparator operably coupled to the photo-diode and the capacitor and configured to generate a first digital signal that is based on a difference between the photo-diode voltage and a threshold voltage associated with the self-referenced latched comparator;
memory that stores operational instructions; and
one or more processing modules that is operably coupled to the self-referenced latched comparator and the memory and configured to execute the operational instructions to process the first digital signal to generate at least one of a second digital signal or a third digital signal that control the at least one of the DAC source current or a DAC sink current

Assignees

• Sigmasense Llc

Inventors

• Huynh Phuong

Classifications

• H10F39/803

  Pixels having integrated switching, control, storage or amplification elements · CPC title

• H03M3/462 Primary

  Details relating to the decimation process (decimation filters in general H03H17/0416, H03H17/0621) · CPC title

• H03M1/0626

  by filtering · CPC title

• H03M3/32

  with special provisions or arrangements for power saving, e.g. by allowing a sleep mode, using lower supply voltage for downstream stages, using multiple clock domains, by selectively turning on stages when needed · CPC title

• H03M3/476

  Non-linear conversion systems · CPC title