Contact and isolation in monolithically stacked VTFET

Patent metadata

Field	Value
Publication number	US-11978796-B2
Application number	US-202117545074-A
Country	US
Kind code	B2
Filing date	Dec 8, 2021
Priority date	Dec 8, 2021
Publication date	May 7, 2024
Grant date	May 7, 2024

Abstract

Monolithically stacked VTFET devices having source/drain contacts with increased contact area and dielectric isolation are provided. In one aspect, a stacked VTFET device includes: at least a bottom VTFET below a top VTFET, wherein the bottom VTFET and the top VTFET each includes source/drain regions interconnected by a vertical fin channel, and a gate stack alongside the vertical fin channel; and source/drain contacts to the source/drain regions, wherein at least one of the source/drain contacts is in direct contact with more than one surface of a given one of the source/drain regions. A stacked VTFET device having at least a bottom VTFET 1 below a top VTFET 1 , and a bottom VTFET 2 below a top VTFET 2 , and a method of forming a stacked VTFET device are also provided.

First claim

What is claimed is:

1. A stacked vertical transport field-effect transistor (VTFET) device, comprising:
at least a bottom VTFET below a top VTFET, wherein the bottom VTFET and the top VTFET each comprises two source/drain regions each vertically connected to a vertical fin channel, and a gate stack alongside the vertical fin channel; and
a first source/drain contact directly contacting a vertical sidewall and a horizontal bottom surface of a bottom source/drain region of the top VTFET.

2. The stacked VTFET device of claim 1 , wherein the vertical fin channel of the bottom VTFET is aligned vertically with the vertical fin channel of the top VTFET.

3. The stacked VTFET device of claim 1 , further comprising:
an isolation layer in between the vertical fin channel of the bottom VTFET and the vertical fin channel of the top VTFET.

4. The stacked VTFET device of claim 3 , wherein the isolation layer comprises a material selected from the group consisting of: silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide nitride (SiCN), and combinations thereof.

5. The stacked VTFET device of claim 3 , further comprising an isolation structure in between the vertical fin channel of the bottom VTFET and the vertical fin channel of the top VTFET, wherein the isolation structure comprises the isolation layer between an upper sacrificial layer and a lower sacrificial layer.

6. The stacked VTFET device of claim 5 , wherein the sacrificial layer comprises silicon germanium (SiGe) having from about 50% germanium (Ge) to about 100% Ge.

7. The stacked VTFET device of claim 5 , wherein the sacrificial layer comprises SiGe65.

8. The stacked VTFET device of claim 3 , wherein the isolation layer is adjacent to the first source/drain contact.

9. The stacked VTFET device of claim 1 , further comprising:
a doped layer adjacent to at least one of the source/drain regions.

10. The stacked VTFET device of claim 9 , wherein the doped layer comprises an n-type dopant or a p-type dopant.

11. The stacked VTFET device of claim 9 , wherein the doped layer comprises a material selected from the group consisting of: phosphorous-doped glass (PSG) and boron-doped glass (BSG).

12. The stacked VTFET device of claim 1 , further comprising a second source/drain contact contacting the vertical sidewall and a horizontal top surface of a top source/drain region of the bottom VTFET.

13. The stacked VTFET device of claim 1 , further comprising a second source/drain contact contacting the vertical sidewall and a horizontal top surface of a top source/drain region of the bottom VTFET.

14. The stacked VTFET device of claim 1 , wherein the top VTFET is a PFET and the bottom VTFET is an NFET.

15. A semiconductor device, comprising:
at least a first bottom vertical transport field effect transistor (VTFET) (bottom VTFET 1 ) below a first top VTFET (top VTFET 1 ), and a second bottom VTFET (bottom VTFET 2 ) below a second top VTFET (top VTFET 2 ), wherein the bottom VTFET 1 , the top VTFET 1 , the bottom VTFET 2 and the top VTFET 2 each comprises at least a gate stack alongside a vertical fin channel and a first source/drain region directly above and a second source/drain region directly below the vertical fin channel;
a first source/drain contact in direct contact with a vertical sidewall and a horizontal bottom surface of the first source/drain region in the top VTFET 1 ; and
a second source/drain contact in direct contact with a vertical sidewall and a horizontal bottom surface of the second source/drain region in the bottom VTFET 2 .

16. The semiconductor device of claim 15 , further comprising:
an isolation layer in between the first source/drain contact and the second source/drain contact, wherein the isolation layer comprises a material selected from the group consisting of: SiN, SiON, SiCN, and combinations thereof.

17. The semiconductor device of claim 15 , further comprising an isolation structure in between the vertical fin channel of the bottom VTFET 2 and the vertical fin channel of the top VTFET 2 , and bottom VTFET and the vertical fin channel of the top VTFET, wherein the isolation structure comprises an isolation layer between an upper sacrificial layer and a lower sacrificial layer.

18. The semiconductor VTFET device of claim 17 , wherein the isolation layer comprises a material selected from the group consisting of: SiN, SiON, SiCN, and combinations thereof, and wherein the upper sacrificial layer and the lower sacrificial layer each comprises silicon germanium (SiGe) having from about 50% germanium (Ge) to about 100% Ge.

19. The stacked VTFET device of claim 15 , further comprising a third source/drain contact in direct contact with the vertical sidewall and a horizontal top surface of the second source/drain region in the bottom VTFET 1 .

20. The stacked VTFET device of claim 15 , wherein the top VTFET 1 is a PFET and the bottom VTFET 1 is an NFET.

Assignees

• IBM

Inventors

• Zhang Chen
• Xie Ruilong
• Yu Lan
• Cheng Kangguo

Classifications

• H10D84/83

  of only insulated-gate FETs [IGFET] · CPC title

• H10D64/252

  for vertical or pseudo-vertical devices · CPC title

• H10D30/025

  of vertical IGFETs (of VDMOS H10D30/0291; of vertical TFTs H10D30/0318) · CPC title

• H10D84/85

  Complementary IGFETs, e.g. CMOS · CPC title

• H10D88/00

  Three-dimensional [3D] integrated devices · CPC title