Electronic structure having two field effect transistors

Patent metadata

Field	Value
Publication number	US-11978744-B2
Application number	US-202117315463-A
Country	US
Kind code	B2
Filing date	May 10, 2021
Priority date	Mar 31, 2017
Publication date	May 7, 2024
Grant date	May 7, 2024

Abstract

A structure is disclosed, comprising: a first field effect transistor, FET, comprising a first source terminal, a first drain terminal, a first layer or body of semiconductive material arranged to provide a first semiconductive channel connecting the first source terminal to the first drain terminal, and a gate terminal arranged with respect to the first semiconductive channel such that a conductivity of the first semiconductive channel may be controlled by application of a voltage to the gate terminal; and a second FET comprising a second source terminal, a second drain terminal, a second layer or body of semiconductive material arranged to provide a second semiconductive channel connecting the second source terminal to the second drain terminal, and the gate terminal, the second conductive channel being arranged with respect to the gate terminal such that a conductivity of the second channel may be controlled by application of a voltage to the gate terminal. Methods of manufacturing such structures are also disclosed.

First claim

The invention claimed is:

1. A structure comprising:
a first field effect transistor, FET, comprising a first source terminal, a first drain terminal, a first layer or body of semiconductive material arranged to provide a first semiconductive channel connecting the first source terminal to the first drain terminal, and a gate terminal arranged over the first semiconductive channel such that a conductivity of the first semiconductive channel is configured to be controlled by application of a voltage to the gate terminal; and
a second FET comprising a second source terminal, a second drain terminal, a second layer or body of semiconductive material arranged to provide a second semiconductive channel connecting the second source terminal to the second drain terminal, and said gate terminal, the second semiconductive channel being arranged over said gate terminal such that a conductivity of the second semiconductive channel is configured to be controlled by application of a voltage to the gate terminal,
wherein the first FET comprises a first layer or body of dielectric material separating the gate terminal from the first layer or body of semiconductive material, and the second FET comprises a second layer or body of dielectric material separating the gate terminal from the second layer or body of semiconductive material,
wherein the first layer or body of semiconductive material, the gate terminal, the second layer or body of semiconductive material, and the first and second layers or bodies of dielectric material are arranged with respect to each other in a stack,
the structure further comprising a third layer of dielectric material arranged to surround the stack and arranged to separate the first source and drain terminals of the first FET from the second source and drain terminals of the second FET,
said third layer of dielectric material having a lower surface, in contact with upper surfaces of the first source and drain terminals, and an upper surface, and wherein at least portions of the second source and drain terminals are formed on said upper surface.

2. The structure in accordance with claim 1 , wherein the first layer or body of semiconductive material comprises a first semiconductive material and the second layer or body of semiconductive material comprises a second semiconductive material, different from said first semiconductive material.

3. The structure in accordance with claim 2 , wherein one of the first and second semiconductive materials is an n-type semiconductor, and the other one of the first and second semiconductive materials is a p-type semiconductor.

4. The structure in accordance with claim 1 , wherein the first layer or body of semiconductive material is arranged to overlap at least one of the first source and drain terminals.

5. The structure in accordance with claim 4 , wherein the first layer or body of semiconductive material is arranged to overlap both of the first source and drain terminals.

6. The structure in accordance with claim 1 , wherein the first layer or body of semiconductive material is arranged not to overlap either of the first source and drain terminals.

7. The structure in accordance with claim 1 , wherein the first layer or body of semiconductive material, the gate terminal, and the second layer or body of semiconductive material are stacked in a nominal vertical direction.

8. The structure in accordance with claim 1 , wherein the gate terminal is substantially planar, and the first layer or body of semiconductive material and the second layer or body of semiconductive material are arranged respectively below and above the gate terminal, spaced from the gate terminal in a direction normal to a plane of the gate terminal.

9. The structure in accordance with claim 1 , wherein the second source terminal and the second drain terminal each comprise a respective via extending through the third layer of dielectric material to contact said second layer or body of semiconductive material.

10. The structure in accordance with claim 1 , further comprising a second gate terminal arranged with respect to the second layer or body of semiconductive material and to which a voltage is configured to be applied to control conductivity of the second semiconductive channel.

11. The structure in accordance with claim 10 , wherein said second gate terminal is arranged above the second semiconductive channel.

12. The structure in accordance with claim 10 , wherein the second gate terminal is separated from the second layer or body of semiconductive material by at least one layer or body of dielectric material.

13. The structure in accordance with claim 1 , further comprising a support arranged to directly support one or more of the first semiconductive channel, and the first source and drain terminals.

14. The structure in accordance with claim 13 , wherein the support comprises one or more of a substrate, and a passivation layer formed on the substrate.

15. The structure in accordance with claim 1 , wherein said third layer of dielectric material is arranged in direct contact with edges of the gate terminal, the first and second layers or bodies of semiconductive material, and the first and second layers or bodies of dielectric material.

16. The structure in accordance with claim 1 , further comprising a fourth layer or body of dielectric material arranged in direct contact with edges of the gate terminal, the first and second layers or bodies of semiconductive material, and the first and second layers or bodies of dielectric material.

17. An electronic circuit comprising a structure in accordance with claim 1 .

Assignees

• Pragmatic Printing Ltd

Inventors

• Price Richard
• Ramsdale Catherine
• Cobb Brian Hardy
• Alkhalil Feras

Classifications

• H10P76/2041

  Photolithographic processes · CPC title

• H10P50/642

  Chemical etching · CPC title

• H10P50/264

  by chemical means · CPC title

• H10P14/6329

  using physical ablation of a target, e.g. physical vapour deposition or pulsed laser deposition · CPC title

• H10P14/44

  Physical vapour deposition [PVD] · CPC title