Methods of manufacturing electronic structures

Patent metadata

Field	Value
Publication number	US-11004875-B2
Application number	US-201816497636-A
Country	US
Kind code	B2
Filing date	Mar 27, 2018
Priority date	Mar 31, 2017
Publication date	May 11, 2021
Grant date	May 11, 2021

Abstract

A structure is disclosed, comprising: a first field effect transistor, FET, comprising a first source terminal, a first drain terminal, a first layer or body of semiconductive material arranged to provide a first semiconductive channel connecting the first source terminal to the first drain terminal, and a gate terminal arranged with respect to the first semiconductive channel such that a conductivity of the first semiconductive channel may be controlled by application of a voltage to the gate terminal; and a second FET comprising a second source terminal, a second drain terminal, a second layer or body of semiconductive material arranged to provide a second semiconductive channel connecting the second source terminal to the second drain terminal, and the gate terminal, the second conductive channel being arranged with respect to the gate terminal such that a conductivity of the second channel may be controlled by application of a voltage to the gate terminal. Methods of manufacturing such structures are also disclosed.

First claim

The invention claimed is:

1. A method of manufacturing an electronic structure comprising a first FET and a second FET, the method comprising:
providing a support;
forming a first layer or body of conductive material on the support;
patterning the first layer or body of conductive material to define a first source terminal, a first drain terminal, and a first gap separating the first source terminal and the first drain terminal;
forming a first layer or body of semiconductive material covering the first source and first drain terminals and filling the gap so as to provide a first semiconductive channel connecting the first source terminal to the first drain terminal;
forming a first layer or body of dielectric material over the first layer or body of semiconductive material;
forming a layer or body of conductive material over the first layer or body of dielectric material;
forming a second layer or body of dielectric material over the layer or body of conductive material;
forming a second layer or body of semiconductive material over the second layer or body of dielectric material;
patterning the first and second layers or bodies of semiconductive material, the first and second layers or bodies of dielectric material, and said layer or body of conductive material to uncover portions of the first source and first drain terminals and produce a stack comprising the first semiconductive channel, a portion of the first layer or body of dielectric material over said first channel, a portion of the layer or body of conductive material over said first channel, a portion of the layer or body of second dielectric material over said first channel, and a portion of the second layer or body of semiconductive material over the first channel;
forming at least one further layer or body of dielectric material over the stack to cover the stack and said uncovered portions of the first source and drain terminals;
patterning the at least one further layer or body of dielectric material to form first and second windows through the at least one further layer or body of dielectric material to said portion of the second layer or body of semiconductive material; and
forming a second source terminal comprising conductive material at least partially filling the first window, and a second drain terminal comprising conductive material at least partially filling the second window, such that said portion of the second layer or body of semiconductive material provides a second semiconductive channel, connecting the second source terminal to the second drain terminal,
whereby the first FET comprises the first source terminal, the first drain terminal, the first channel, and said portion of the layer or body of conductive material, the second FET comprises the second source terminal, the second drain terminal, the second channel, and said portion of the layer or body of conductive material.

2. A method in accordance with claim 1 , wherein said stack overlaps at least one of the first source and first drain terminals.

3. A method in accordance with claim 2 , wherein said stack overlaps both of the first source and first drain terminals.

4. A method in accordance with claim 3 , wherein said first window is positioned above a portion of the first source terminal overlapped by the stack and said second window is positioned above a portion of the first drain terminal overlapped by the stack.

5. A method in accordance with claim 1 , wherein said stack does not overlap either the first source or the first drain terminal.

6. A method in accordance with claim 1 , wherein said patterning the at least one further layer or body of dielectric material to form first and second windows further comprises forming at least one of a third window down to a gate terminal and a fourth window down to one of the first source terminal and the first drain terminal.

7. A method of manufacturing an electronic structure comprising a first FET and a second FET, the method comprising:
providing a support;
forming a first layer or body of conductive material on the support;
patterning the first layer or body of conductive material to define a first source terminal, a first drain terminal, and a first gap separating the first source terminal and the first drain terminal;
forming a first layer or body of semiconductive material covering the first source and first drain terminals and filling the gap so as to provide a first semiconductive channel connecting the first source terminal to the first drain terminal;
forming a first layer or body of dielectric material over the first layer or body of semiconductive material;
forming a layer or body of conductive material over the first layer or body of dielectric material;
patterning the first layer or body of semiconductive material, the first layer or body of dielectric material, and said layer or body of conductive material to uncover at least portions of the first source and first drain terminals and produce a first stack comprising the first semiconductive channel, a portion of the first layer or body of dielectric material over said first channel, and a portion of the layer or body of conductive material over said first channel;
forming a second layer or body of dielectric material over the first stack and uncovered portions of the first source and first drain terminals;
forming a second layer or body of semiconductive material over the second layer or body of dielectric material;
patterning the second layer or body of semiconductive material and the second layer or body of dielectric material to uncover at least portions of the first source and first drain terminals and produce a second stack comprising the first semiconductive channel, said portion of the first layer or body of dielectric material over said first channel, said portion of the layer or body of conductive material over said first channel, a portion of the layer or body of second dielectric material over said first channel, and a portion of the second layer or body of semiconductive material over the first channel;
forming at least one further layer or body of dielectric material over the second stack to cover the second stack and said uncovered portions of the first source and drain terminals;
patterning the at least one further layer or body of dielectric material to form first and second windows through the at least one further layer or body of dielectric material to said portion of the second layer or body of semiconductive material;
forming a second source terminal comprising conductive material at least partially filling the first window, and a second drain terminal comprising conductive material at least partially filling the second window, such that said portion of the second layer or body of semiconductive material provides a second semiconductive channel, connecting the second source terminal to the second drain terminal,
whereby the first FET comprises the first source terminal, the first drain terminal, the first channel, and said portion of the layer or body of conductive material, the second FET comprises the second source terminal, the second drain terminal, the second channel, and said portion of the layer or body of conductive material.

8. A method in accordance with claim 7 , wherein said patterning to uncover at least portions of the first source and first drain terminals and produce said first stack comprises forming a layer of photoresist over said layers to be patterned to produce the first stack, exposing the structure from below with electromagnetic radiation such that the first source and first drain terminals shield portions of the photoresist from said radiation and a portion of the photoresist above the first semiconductive channel is exposed, processing the phot

Assignees

• Pragmatic Printing Ltd

Inventors

• Price Richard
• Ramsdale Catherine
• Cobb Brian Hardy
• Alkhalil Feras

Classifications

• H10P76/2041

  Photolithographic processes · CPC title

• H10P50/642

  Chemical etching · CPC title

• H10P50/264

  by chemical means · CPC title

• H10P14/6329

  using physical ablation of a target, e.g. physical vapour deposition or pulsed laser deposition · CPC title

• H10P14/44

  Physical vapour deposition [PVD] · CPC title