Issuing a sequence of instructions including a condition-dependent instruction

Patent metadata

Field	Value
Publication number	US-11977896-B2
Application number	US-202217942554-A
Country	US
Kind code	B2
Filing date	Sep 12, 2022
Priority date	Sep 12, 2022
Publication date	May 7, 2024
Grant date	May 7, 2024

Abstract

An apparatus, method and computer program, the apparatus comprising processing circuitry to execute instructions, issue circuitry to issue the instructions for execution by the processing circuitry, and candidate instruction storage circuitry to store a plurality of condition-dependent instructions, each specifying at least one condition. The issue circuitry is configured to issue a given condition-dependent instruction in response to a determination or a prediction of the at least one condition specified by the given condition-dependent instruction being met, and when the given condition-dependent instruction is a sequence-start instruction, the issue circuitry is responsive to the determination or prediction to issue a sequence of instructions comprising the sequence-start instruction and at least one subsequent instruction.

First claim

We claim:

1. An apparatus comprising:
processing circuitry to execute instructions;
issue circuitry to issue the instructions for execution by the processing circuitry; and
candidate instruction storage circuitry to store a plurality of condition-dependent instructions, each specifying at least one condition,
wherein:
the issue circuitry is configured to issue a given condition-dependent instruction in response to a determination or a prediction of the at least one condition specified by the given condition-dependent instruction being met; and
when the given condition-dependent instruction is a sequence-start instruction, the issue circuitry is responsive to the determination or prediction to issue a sequence of instructions comprising the sequence-start instruction and at least one subsequent instruction.

2. The apparatus of claim 1 , wherein:
the plurality of condition-dependent instructions comprise a pool of candidate condition-dependent instructions; and
the issue circuitry comprises instruction selection circuitry to perform a selection process to:
determine whether the at least one condition specified by any of the condition-dependent instructions in the pool of candidate condition-dependent instructions has been or is predicted to have been met; and
select, in dependence on whether the at least one condition specified by any of the condition-dependent instructions in the pool of candidate condition-dependent instructions has been or is predicted to have been met, a next instruction to issue, the next instruction being selected from the pool of candidate condition-dependent instructions.

3. The apparatus of claim 1 , wherein
an encoding of the at least one subsequent instruction excludes a condition field indicating the at least one condition.

4. The apparatus of claim 1 , wherein:
each condition-dependent instruction specifies state update information indicative of a state update for use in evaluating whether the at least one condition specified by one or more of the plurality of condition-dependent instructions has been met; and
an encoding of the at least one subsequent instruction excludes a state update field indicating the state update information.

5. The apparatus of claim 1 , wherein
the sequence-start instruction specifies information indicative of a location at which one or more of the at least one subsequent instruction is stored.

6. The apparatus of claim 1 , wherein
a number of bits in each of the at least one subsequent instruction is less than a number of bits in each of the plurality of condition-dependent instructions.

7. The apparatus of claim 1 , wherein
the issue circuitry is configured to suppress interrupting issuing the sequence of instructions by issuing a further condition-dependent instruction before all of the instructions in the sequence have been issued.

8. The apparatus of claim 1 , wherein
the issue circuitry is responsive to interrupt permission information specified by the sequence-start instruction to determine whether it is permitted to interrupt issuing the sequence of instructions to issue a further condition-dependent instruction before all of the instructions in the sequence have been issued.

9. The apparatus of claim 8 , wherein
the issue circuitry is configured, in response to determining that it is permitted to interrupt issuing the sequence of instructions, to determine, based on an instruction priority order associated with the sequence-start instruction and the further condition-dependent instruction, whether to interrupt issuing the sequence of instructions by issuing the further condition-dependent instruction.

10. The apparatus of claim 8 , comprising
sequence state storage circuitry to store sequence state to enable execution of the sequence of instructions to restart after issuing the sequence of instructions is interrupted.

11. The apparatus of claim 1 , wherein
the issue circuitry comprises condition prediction circuitry to suppress, in response to a speculation suppression indication identified by the sequence-start instruction, speculation of whether the at least one condition specified by the sequence-start instruction has been met.

12. The apparatus of claim 1 , wherein
the issue circuitry is configured to control a timing of issuing the sequence-start instruction based on analysis of dependencies specified by one or more of the at least one subsequent instruction.

13. The apparatus of claim 1 , comprising
counter circuitry to maintain one or more hardware counters,
wherein when an instruction specifies a counter-advance indication in addition to identifying a data processing operation to be performed, the processing circuitry is responsive to the counter-advance indication to issue a counter advance signal to trigger the counter circuitry to advance a count value of at least one of the one or more hardware counters.

14. The apparatus of claim 13 , wherein
for at least one encoding of condition information indicating the at least one condition specified by each of the plurality of condition-dependent instructions, the issue circuitry is configured to determine whether the at least one condition is met depending on whether a counter event has occurred for a given hardware counter maintained by the counter circuitry.

15. The apparatus of claim 14 , wherein
the counter event comprises a detection of at least one of:
an overflow signal asserted by the counter circuitry in response to an overflow event; and
a secondary event signal asserted by the counter circuitry in response to the count value being advanced to a predetermined value.

16. The apparatus of claim 13 , wherein
the processing circuitry is responsive to at least one encoding of an instruction to use the count value as an operand or to calculate a register identifier to identify a source register or a destination register.

17. The apparatus of claim 13 , comprising
configuration data storage circuitry to store counter configuration information associated with the counter circuitry,
wherein:
the counter circuitry is responsive to the counter advance signal to determine an updated count value based on the counter configuration information; and
the counter configuration information is indicative of at least one of:
an advancement amount to be applied to the count value; and
a top count value of the counter.

18. The apparatus of claim 13 , wherein:
the counter circuitry is configured to maintain a plurality of hardware counters; and
when a chain overflow indication associated with a first hardware counter and a second hardware counter is set, the counter circuitry is responsive to a counter overflow event associated with the first hardware counter to advance the second hardware counter.

19. A method comprising:
issuing instructions for execution by processing circuitry;
storing a plurality of condition-dependent instructions, each specifying at least one condition,
issuing a given condition-dependent instruction in response to a determination or a prediction of the at least one condition specified by the given condition-dependent instruction being met; and
in response to the given condition-dependent instruction being a sequence-start instruction, issuing, in response to the determination or the prediction, a sequence of instructions comprising the sequence-start instruction and at least one subsequent instruction.

20. A non-transitory computer-readable storage medium storing a computer program comprising instructions which, when

Assignees

• Advanced Risc Mach Ltd

Inventors

• Walker Matthew James
• Eyole Mbou
• Gabrielli Giacomo
• VENU Balaji
• Wang Wei

Classifications

• G06F15/825

  Dataflow computers · CPC title

• G06F9/3856 Primary

  Reordering of instructions, e.g. using queues or age tags · CPC title

• G06F9/30145

  Instruction analysis, e.g. decoding, instruction word fields · CPC title

• G06F9/32

  Address formation of the next instruction, e.g. by incrementing the instruction counter (G06F9/38 takes precedence) · CPC title

• G06F9/3836

  Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution · CPC title