ToF system

Patent metadata

Field	Value
Publication number	US-11977186-B2
Application number	US-202117341084-A
Country	US
Kind code	B2
Filing date	Jun 7, 2021
Priority date	Jun 7, 2021
Publication date	May 7, 2024
Grant date	May 7, 2024

Abstract

In an embodiment, a method includes: resetting respective count values of a plurality of analog counters to an initial count value, each analog counter of the plurality of analog counters corresponding to a histogram bin of a time-of-flight (ToF) histogram; after resetting the respective count values, receiving a plurality of digital addresses from a time-to-digital converter (TDC); during an integration period, for each received digital address, selecting one analog counter based on the received digital address, and changing the respective count value of the selected one analog counter towards a second count value by a discrete amount, where each analog counter has a final count value at an end of the integration period; and after the integration period, determining an associated final bin count of each histogram bin of the ToF histogram based on the final count value of the corresponding analog counter.

First claim

What is claimed is:

1. A method comprising:
resetting respective count values of a plurality of analog counters to an initial count value, each analog counter of the plurality of analog counters corresponding to a histogram bin of a time-of-flight (ToF) histogram;
after resetting the respective count values of the plurality of analog counters, receiving a plurality of digital addresses from a time-to-digital converter (TDC), the TDC having an input coupled to a single photon avalanche diode (SPAD);
during an integration period, for each received digital address of the plurality of digital addresses, selecting one analog counter of the plurality of analog counters based on the received digital address, and changing the respective count value of the selected one analog counter towards a second count value by a discrete amount, the second count value being different than the initial count value, wherein each analog counter has a final count value at an end of the integration period; and
after the integration period, determining an associated final bin count of each histogram bin of the ToF histogram based on the final count value of the corresponding analog counter.

2. The method of claim 1 , wherein the initial count value corresponds to a first voltage, wherein the second count value corresponds to a second voltage that is different than the first voltage, wherein resetting the respective count values of the plurality of analog counters comprises resetting a voltage of an associated storage capacitor of each analog counter to the first voltage, and wherein changing the count value of the selected one analog counter comprises changing the voltage of the associated storage capacitor by a discrete voltage towards the second voltage.

3. The method of claim 2 , wherein the first voltage corresponds to a full-scale voltage that is higher than the second voltage, and wherein changing the voltage of the associated storage capacitor by the discrete voltage towards the second voltage comprises decreasing the voltage of the associated storage capacitor by the discrete voltage towards the second voltage.

4. The method of claim 2 , further comprising, after the integration period and during a signal conversion period, determining an associated remaining bin count of each histogram bin of the ToF histogram, wherein determining the associated remaining bin count of each histogram bin comprises:
providing a plurality of pulses to an input of each analog counter; and
for each analog counter, counting an associated remaining number of pulses until the voltage of the associated storage capacitor reaches the second voltage, wherein the associated remaining bin count of each histogram bin is equal to the associated remaining number of pulses of the corresponding analog counter, wherein determining the associated final bin count of each histogram bin comprises determining the associated final bin count of each histogram bin based on the associated remaining bin count.

5. The method of claim 4 , further comprising, after the signal conversion period, resetting the voltage of the storage capacitor of each analog counter to the first voltage, and determining an associated full-scale bin count for each histogram bin, wherein determining the associated full-scale bin count for each histogram bin comprises:
providing a plurality of pulses to the input of each analog counter; and
for each analog counter, counting an associated total number of pulses until the voltage of the associated storage capacitor reaches the second voltage from the first voltage, wherein the associated full-scale bin count of each histogram bin is equal to the associated total number of pulses of the corresponding analog counter, and wherein determining the associated final bin count of each histogram bin is further based on the associated full-scale bin count.

6. The method of claim 5 , wherein a ripple counter is used for counting each of the associated remaining number of pulses and each of the associated total number of pulses, and wherein determining the associated final bin count of each histogram bin comprises:
latching the associated remaining bin count into a count latch; and
using an adder to subtract a content of the count latch from an output of the ripple counter to obtain the associated final bin count.

7. The method of claim 1 , wherein each of the plurality of digital addresses comprises m bits, m being a positive integer greater than or equal to 1, wherein the plurality of analog counters comprises n analog counters, n being equal to 2 m , and wherein selecting the one analog counter comprises using a decoder having n outputs respectively coupled to the n analog counters, and a decoder input for receiving the plurality of digital addresses.

8. The method of claim 7 , wherein the decoder comprises a low-voltage digital signal (LVDS) latch.

9. The method of claim 7 , wherein the decoder input is coupled to an output of a low-voltage digital signal (LVDS) latch.

10. The method of claim 7 , wherein m is equal to 1 and n is equal to 2.

11. The method of claim 1 , wherein the TDC comprises a low-voltage digital signal (LVDS) latch.

12. The method of claim 11 , wherein the each of the plurality of digital addresses comprises 1-bit, wherein the plurality of analog counters comprises first and second analog counters, and wherein the LVDS latch comprises a first output coupled to the first analog counter and a second output coupled to the second analog counter.

13. A time-of-flight (ToF) system comprising:
a plurality of single photon avalanche diodes (SPADs) configured to generate SPAD events;
a plurality of time-to-digital converters (TDCs) coupled to the plurality of SPADs, wherein each TDC of the plurality of TDCs is configured to generate digital addresses based on SPAD events generated by an associated SPAD of the plurality of SPADs;
a plurality of histogram generation circuits, each histogram generation circuit of the plurality of histogram generation circuits coupled to a respective TDC of the plurality of TDCs, wherein each histogram generation circuit comprises:
an addressing logic circuit having a plurality of outputs, and an input configured to receive digital addresses from the respective TDC,
a plurality of analog counters, wherein each analog counter of the plurality of analog counters comprises an input coupled to a respective output of the plurality of outputs of the addressing logic circuit, wherein each analog counter comprises an associated storage capacitor; and

an analog-to-digital converter (ADC) coupled to the plurality of analog counters, wherein:
each histogram generation circuit is configured to reset a voltage of the associated storage capacitor of each analog counter to a first voltage,
the addressing logic circuit is configured to, during an integration period after the resetting of the plurality of analog counters, select, for each received digital address, one analog counter of the plurality of analog counters based on the received digital address, and assert the input of the selected one analog counter, wherein the selected one analog counter is configured to change a voltage of the associated storage capacitor of the selected one analog counter towards a second voltage by a discrete voltage when the input of the selected one analog counter is asserted, wherein the associated storage capacitor of each analog counter is configured to have a final voltage at an end of the integration period, and
the ADC is configured to convert the final voltage of the associated storage capacitor of each analog counter to a corresponding digital count, wherein each digital count is a

Assignees

• St Microelectronics Res & Dev Ltd

Inventors

• Buckbee Kasper
• Dutton Neale

Classifications

• G01S7/4865 Primary

  Time delay measurement, e.g. time-of-flight measurement, time of arrival measurement or determining the exact position of a peak (peak detection in noise, signal conditioning G01S7/487) · CPC title

• G01S7/4863

  Detector arrays, e.g. charge-transfer gates · CPC title

• H03M1/34

  Analogue value compared with reference values (H03M1/48 takes precedence) · CPC title

• G01C3/00

  Measuring distances in line of sight; Optical rangefinders (tapes, chains or wheels for measuring length G01B3/00; active triangulation systems, i.e. using the transmission and reflection of electromagnetic waves other than radio waves, G01S17/48) · CPC title

• G01C3/06

  Use of electric means to obtain final indication · CPC title